[PATCH] D125270: [riscv] Remove mutation of prior vsetvli from insertion dataflow

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:484
+  Register AVLReg = MI.getOperand(1).getReg();
+  return DestReg == RISCV::X0 && AVLReg == RISCV::X0;
+}
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Since it's PseudoVSETVLIX0 can we move AVLReg == RISCV::X0 to an assert?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125270/new/

https://reviews.llvm.org/D125270