[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle requested changes to this revision.
nhaehnle added a comment.

I don't think the premise of this patch is correct. A source-level `writelane` intrinsic is **not** allowed to overwrite inactive lanes. If it does, then that's UB. If you want wave-wide `writelane` in source, the way to achieve that would be to use WWM.

Also, the name "lane VGPRs" is misleading. Isn't more like "wave-wide VGPRs", actually?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192