[PATCH] D126288: [TableGen] Do not crash on insufficient positional instruction operands.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev created this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126288

Files:
  llvm/test/TableGen/InsufficientPositionalOperands.td
  llvm/utils/TableGen/CodeEmitterGen.cpp


Index: llvm/utils/TableGen/CodeEmitterGen.cpp
===================================================================
--- llvm/utils/TableGen/CodeEmitterGen.cpp
+++ llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -118,16 +118,16 @@
               (!NamedOpIndices.empty() && NamedOpIndices.count(
                 CGI.Operands.getSubOperandNumber(NumberedOp).first)))) {
       ++NumberedOp;
+    }
 
-      if (NumberedOp >= CGI.Operands.back().MIOperandNo +
-                        CGI.Operands.back().MINumOperands) {
-        errs() << "Too few operands in record " << R->getName() <<
-                  " (no match for variable " << VarName << "):\n";
-        errs() << *R;
-        errs() << '\n';
+    if (NumberedOp >=
+        CGI.Operands.back().MIOperandNo + CGI.Operands.back().MINumOperands) {
+      errs() << "Too few operands in record " << R->getName()
+             << " (no match for variable " << VarName << "):\n";
+      errs() << *R;
+      errs() << '\n';
 
-        return;
-      }
+      exit(1);
     }
 
     OpIdx = NumberedOp++;
Index: llvm/test/TableGen/InsufficientPositionalOperands.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/InsufficientPositionalOperands.td
@@ -0,0 +1,30 @@
+// RUN: not llvm-tblgen -gen-emitter -I %p/../../include %s 2>&1 | FileCheck %s
+
+// Check that TableGen doesn't crash on insufficient positional
+// instruction operands.
+
+include "llvm/Target/Target.td"
+
+def ArchInstrInfo : InstrInfo { }
+
+def Arch : Target {
+  let InstructionSet = ArchInstrInfo;
+}
+
+def Reg : Register<"reg">;
+
+def Regs : RegisterClass<"foo", [i32], 0, (add Reg)>;
+
+def foo : Instruction {
+  bits<3> rd;
+  bits<3> rs;
+
+  bits<8> Inst;
+  let Inst{1-0} = 0;
+  let Inst{4-2} = rd;
+  let Inst{7-5} = rs;
+
+// CHECK: Too few operands in record foo (no match for variable rs)
+  let OutOperandList = (outs Regs:$xd);
+  let InOperandList = (ins);
+}


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