[PATCH] D126275: [LegalizeTypes][VP] Add integer promote support for vp.gather and vp.scatter

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll:13
+; RV32-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; RV32-NEXT:    vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT:    vmv1r.v v8, v9
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craig.topper wrote:
> This isn't correct code for the IR. This is loading 32 bit elements from memory, but the memory value is only 7 bits.
Oops. I guess it's reading 8 bit elements. So maybe it's ok.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126275/new/

https://reviews.llvm.org/D126275