[llvm] 569d894 - [DAGCombiner][AArch64] Don't fold (smulo x, 2) -> (saddo x, x) if VT is i2.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-05-23T11:13:57-07:00
New Revision: 569d8945f311e76b25925ff4b4257734711d9e2f

URL: https://github.com/llvm/llvm-project/commit/569d8945f311e76b25925ff4b4257734711d9e2f
DIFF: https://github.com/llvm/llvm-project/commit/569d8945f311e76b25925ff4b4257734711d9e2f.diff

LOG: [DAGCombiner][AArch64] Don't fold (smulo x, 2) -> (saddo x, x) if VT is i2.

If the VT is i2, then 2 is really -2.

Test has not been commited yet, but diff shows the change.

Fixes PR55644.

Differential Revision: https://reviews.llvm.org/D126213

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/AArch64/pr55644.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 958f2dbc61459..61d23aeec06ea 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4913,7 +4913,9 @@ SDValue DAGCombiner::visitMULO(SDNode *N) {
                      DAG.getConstant(0, DL, CarryVT));
 
   // (mulo x, 2) -> (addo x, x)
-  if (N1C && N1C->getAPIntValue() == 2)
+  // FIXME: This needs a freeze.
+  if (N1C && N1C->getAPIntValue() == 2 &&
+      (!IsSigned || VT.getScalarSizeInBits() > 2))
     return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL,
                        N->getVTList(), N0, N0);
 

diff  --git a/llvm/test/CodeGen/AArch64/pr55644.ll b/llvm/test/CodeGen/AArch64/pr55644.ll
index ac98de13c6f07..00d29d700cea1 100644
--- a/llvm/test/CodeGen/AArch64/pr55644.ll
+++ b/llvm/test/CodeGen/AArch64/pr55644.ll
@@ -5,9 +5,10 @@ define i1 @f(i2 %0) {
 ; CHECK-LABEL: f:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sbfx w8, w0, #0, #2
-; CHECK-NEXT:    add w8, w8, w8
-; CHECK-NEXT:    lsl w9, w8, #30
-; CHECK-NEXT:    cmp w8, w9, asr #30
+; CHECK-NEXT:    lsl w8, w8, #1
+; CHECK-NEXT:    neg w9, w8
+; CHECK-NEXT:    lsl w9, w9, #30
+; CHECK-NEXT:    cmn w8, w9, asr #30
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %2 = call { i2, i1 } @llvm.smul.with.overflow.i2(i2 %0, i2 -2)