[PATCH] D126213: [DAGCombiner][AArch64] Don't fold (smulo x, 2) -> (saddo x, x) if VT is i2.

[Sanjay Patel via Phabricator via llvm-commits]

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.

LGTM - I don't think we'd see this problem in IR with the example test because we'd reduce the intrinsic if there's no use of the multiply result. We probably don't have the corresponding fold here because we don't expect to create these ops in SDAG?


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