[PATCH] D125601: [DAGCombiner][AArch64] Reorder the bitcast of scalable vector

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Hi @Allen, Sorry for the delay but my investigations turned more complex than I had expected.  I don't believe this is a DAG level problem and the real issue here is that 64/128bit fixed length extracts from unpacked scalable vectors are not legal and thus common legalisation code kicks in to perform the operation via the stack. The solution is to be able to directly isel these operations.  It turns out this is not straight forward.  I've uploaded D126201 <https://reviews.llvm.org/D126201>, which is clearly a bit of a hack, to show the areas to investigate.

The main problem is the current definition of `extract_subvector` does not allow mixed (i.e. fixed and scalable) vector types.  Although it can be changed, this causes build failures because many existing patterns need to be updated because their types can no longer be inferred.  Instead I propose a specific node, currently called `extract_subvector2` which is specifically for the case where you want to extract a fixed length vector from a scalable vector.  My reasoning being no existing patterns need to change and it makes it easier to see these sorts of extracts that typically need special handling. I didn't manage to figure out why I need to disable the existing `extract_subvector` patterns, which for some reason kept matching even though the types do not match what those patterns require.

Let me know how you want to proceed. Feel free to run with `D126201` or you can wait on me to create a proper implementation.  It just depend on you timeline as I'm not sure how much time I'll be able to invest in this over the next few weeks.


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  https://reviews.llvm.org/D125601/new/

https://reviews.llvm.org/D125601