[llvm] 6ef5e24 - [AArch64] Fix assumptions on input type of tryCombineFixedPointConvert

[David Green via llvm-commits]

Author: David Green
Date: 2022-05-23T08:55:54+01:00
New Revision: 6ef5e242f2f7a307c4f4ab9c9310410d1acba6a7

URL: https://github.com/llvm/llvm-project/commit/6ef5e242f2f7a307c4f4ab9c9310410d1acba6a7
DIFF: https://github.com/llvm/llvm-project/commit/6ef5e242f2f7a307c4f4ab9c9310410d1acba6a7.diff

LOG: [AArch64] Fix assumptions on input type of tryCombineFixedPointConvert

It is possible for the input type to not be v2i64 or v4i32, so weaken
the assertion to a return, fixing the crash in the new test.

Fixes #55606

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f3f10c60447e2..e21de4c6270ff 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15109,7 +15109,7 @@ static SDValue tryCombineFixedPointConvert(SDNode *N,
   else if (Vec.getValueType() == MVT::v2i64)
     VecResTy = MVT::v2f64;
   else
-    llvm_unreachable("unexpected vector type!");
+    return SDValue();
 
   SDValue Convert =
       DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);

diff  --git a/llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll b/llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
index b068edc066760..b580c4921fb66 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
@@ -40,8 +40,21 @@ entry:
   ret double %vcvtd_n_f64_s64
 }
 
+define float @do_stuff(<8 x i16> noundef %var_135) {
+; CHECK-LABEL: do_stuff:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umaxv.8h h0, v0
+; CHECK-NEXT:    ucvtf s0, s0, #1
+; CHECK-NEXT:    ret
+entry:
+  %vmaxv.i = call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %var_135) #2
+  %vcvts_n_f32_u32 = call float @llvm.aarch64.neon.vcvtfxu2fp.f32.i32(i32 %vmaxv.i, i32 1)
+  ret float %vcvts_n_f32_u32
+}
+
 declare <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64>, <1 x i64>, i32)
 declare double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64, i32)
 declare <1 x double> @llvm.nearbyint.v1f64(<1 x double>)
 declare i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double)
-
+declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>) #1
+declare float @llvm.aarch64.neon.vcvtfxu2fp.f32.i32(i32, i32) #1