[llvm] 768a1ca - [SelectionDAG] Fold abs(undef) to 0 instead of undef.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-05-22T12:47:32-07:00
New Revision: 768a1ca5eccb678947f4155e38a5f5744dcefb56

URL: https://github.com/llvm/llvm-project/commit/768a1ca5eccb678947f4155e38a5f5744dcefb56
DIFF: https://github.com/llvm/llvm-project/commit/768a1ca5eccb678947f4155e38a5f5744dcefb56.diff

LOG: [SelectionDAG] Fold abs(undef) to 0 instead of undef.

abs should only produce a positive value or the signed minimum
value. This means we can't fold abs(undef) to undef as that would
allow more values. Fold to 0 instead to match InstSimplify.

Fixes test mentioned in comment on pr55271.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D126174

Added: 
    llvm/test/CodeGen/X86/pr55271.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 6ddf1ceef647e..09c9d4179ae13 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5243,7 +5243,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     assert(VT.isInteger() && VT == Operand.getValueType() &&
            "Invalid ABS!");
     if (OpOpcode == ISD::UNDEF)
-      return getUNDEF(VT);
+      return getConstant(0, DL, VT);
     break;
   case ISD::BSWAP:
     assert(VT.isInteger() && VT == Operand.getValueType() &&

diff  --git a/llvm/test/CodeGen/X86/pr55271.ll b/llvm/test/CodeGen/X86/pr55271.ll
new file mode 100644
index 0000000000000..3ffa6cf4acb80
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr55271.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+; abs(undef) should fold to 0 not undef.
+
+declare i32 @llvm.abs.i32(i32, i1 immarg) #0
+
+define i32 @abs(i32 %0) {
+; CHECK-LABEL: abs:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    retq
+  %2 = call i32 @llvm.abs.i32(i32 undef, i1 false)
+  ret i32 %2
+}