[PATCH] D126118: [ARM] Fix vcvtb/t.f16 input liveness

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
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The `vcvtb.f16.f32 Sd, Sn` (and `vcvtt.f16.f32`) instruction convert a f32 into a f16, writing either the top or bottom halves of the register. That means that half of the input register Sd is used in the output. This wasn't being modelled in the instructions, leading later analyses to believe that the registers were dead where they were not, generating invalid assembly.

Fix that be specifying the input Sda register for the instructions too, allowing them to be set for cases like vector inserts. Most of the changes are plumbing through the constraint string.`§


https://reviews.llvm.org/D126118

Files:
  llvm/lib/Target/ARM/ARMInstrFormats.td
  llvm/lib/Target/ARM/ARMInstrVFP.td
  llvm/test/CodeGen/ARM/aes-erratum-fix.ll
  llvm/test/CodeGen/Thumb2/mve-div-expand.ll
  llvm/test/CodeGen/Thumb2/mve-fmath.ll
  llvm/test/CodeGen/Thumb2/mve-masked-store.ll
  llvm/test/CodeGen/Thumb2/mve-vcvt.ll
  llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

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