[PATCH] D126074: [AMDGPU] Mark SMEM cache invalidations as not reading memory

[Jay Foad via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9af56c676e40: [AMDGPU] Mark SMEM cache invalidations as not reading memory (authored by foad).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126074/new/

https://reviews.llvm.org/D126074

Files:
  llvm/lib/Target/AMDGPU/SMInstructions.td
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll


Index: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
+++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
@@ -14,7 +14,7 @@
 
 ; VI-LABEL: {{^}}test_s_dcache_wb_vol_insert_wait:
 ; VI-NEXT: ; %bb.0:
-; VI-NEXT: s_dcache_wb_vol
+; VI: s_dcache_wb_vol
 ; VI: s_waitcnt lgkmcnt(0) ; encoding
 define amdgpu_kernel void @test_s_dcache_wb_vol_insert_wait() #0 {
   call void @llvm.amdgcn.s.dcache.wb.vol()
Index: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
+++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
@@ -14,7 +14,7 @@
 
 ; VI-LABEL: {{^}}test_s_dcache_wb_insert_wait:
 ; VI-NEXT: ; %bb.0:
-; VI-NEXT: s_dcache_wb
+; VI: s_dcache_wb
 ; VI: s_waitcnt lgkmcnt(0) ; encoding
 define amdgpu_kernel void @test_s_dcache_wb_insert_wait() #0 {
   call void @llvm.amdgcn.s.dcache.wb()
Index: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
+++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
@@ -16,7 +16,7 @@
 
 ; GCN-LABEL: {{^}}test_s_dcache_inv_vol_insert_wait:
 ; GCN-NEXT: ; %bb.0:
-; GCN-NEXT: s_dcache_inv_vol
+; GCN: s_dcache_inv_vol
 ; GCN: s_waitcnt lgkmcnt(0) ; encoding
 define amdgpu_kernel void @test_s_dcache_inv_vol_insert_wait() #0 {
   call void @llvm.amdgcn.s.dcache.inv.vol()
Index: llvm/lib/Target/AMDGPU/SMInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SMInstructions.td
+++ llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -220,6 +220,7 @@
 class SM_Inval_Pseudo <string opName, SDPatternOperator node = null_frag> : SM_Pseudo<
   opName, (outs), (ins), "", [(node)]> {
   let hasSideEffects = 1;
+  let mayLoad = 0;
   let mayStore = 0;
   let has_sdst = 0;
   let has_sbase = 0;


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