[PATCH] D126064: [AMDGPU] Handle mandatory literals in isOperandLegal
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 20 08:17:11 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG78ec59e6aea9: [AMDGPU] Handle mandatory literals in isOperandLegal (authored by foad).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D126064/new/
https://reviews.llvm.org/D126064
Files:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
Index: llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
+++ llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
@@ -1,13 +1,12 @@
-; RUN: not --crash llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s 2>&1 | FileCheck %s -check-prefix GFX10
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX10
declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float)
declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg)
-; FIXME: This instruction uses two different literal constants which is not
-; allowed.
+; Check that this constant is not folded into the v_fmaak_f32 instruction.
; GFX10-LABEL: _amdgpu_ps_main:
-; GFX10: Bad machine code: VOP2/VOP3 instruction uses more than one literal
-; GFX10: instruction: %4:vgpr_32 = nnan nsz arcp contract afn reassoc nofpexcept V_FMAAK_F32 1078530011, %0:vgpr_32, -1077342245, implicit $mode, implicit $exec
+; GFX10: v_mov_b32_e32 v1, 0x40490fdb
+; GFX10: v_fmaak_f32 v1, v0, v1, 0xbfc90fdb
define amdgpu_ps void @_amdgpu_ps_main(float %arg) {
bb:
%i = fmul reassoc nnan nsz arcp contract afn float %arg, 0x400921FB60000000
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4965,9 +4965,9 @@
MO = &MI.getOperand(OpIdx);
int ConstantBusLimit = ST.getConstantBusLimit(MI.getOpcode());
- int VOP3LiteralLimit = ST.hasVOP3Literal() ? 1 : 0;
+ int LiteralLimit = !isVOP3(MI) || ST.hasVOP3Literal() ? 1 : 0;
if (isVALU(MI) && usesConstantBus(MRI, *MO, OpInfo)) {
- if (isVOP3(MI) && isLiteralConstantLike(*MO, OpInfo) && !VOP3LiteralLimit--)
+ if (isLiteralConstantLike(*MO, OpInfo) && !LiteralLimit--)
return false;
SmallDenseSet<RegSubRegPair> SGPRsUsed;
@@ -4986,12 +4986,10 @@
return false;
SGPRsUsed.insert(SGPR);
}
- } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
- if (--ConstantBusLimit <= 0)
- return false;
- } else if (isVOP3(MI) && AMDGPU::isSISrcOperand(InstDesc, i) &&
- isLiteralConstantLike(Op, InstDesc.OpInfo[i])) {
- if (!VOP3LiteralLimit--)
+ } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32 ||
+ (AMDGPU::isSISrcOperand(InstDesc, i) &&
+ isLiteralConstantLike(Op, InstDesc.OpInfo[i]))) {
+ if (!LiteralLimit--)
return false;
if (--ConstantBusLimit <= 0)
return false;
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