[PATCH] D125364: [RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:822
+                                   (vti.Vector vti.RegClass:$rs2),
+                                   (vti.Mask true_mask), X0)),
+                  (wti.Vector (riscv_fpextend_vl_oneuse
----------------
Using `V0` in VL patterns is uncommon. We do it twice but I'm not entirely sure why or if that's an oversight. Shouldn't we be using `VLOpFrag` and `GPR:$vl`?


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  https://reviews.llvm.org/D125364/new/

https://reviews.llvm.org/D125364