[PATCH] D126040: [InstCombine] Fold a mul with bool value into and

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp:383
+    if ((XKnown.countMaxPopulation() == 1) &&
+        (YKnown.countMaxPopulation() == 1))
+      return BinaryOperator::CreateAnd(Op0, Op1);
----------------
this doesn't limit to 0 / 1 - it means at most 1 bit is set - so 0 or any-pow-2

KnownBits::getMaxValue().ule(1) might be what you want?


================
Comment at: llvm/test/Transforms/InstCombine/mull.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
----------------
Maybe rename this file mul-bool.ll ?


================
Comment at: llvm/test/Transforms/InstCombine/mull.ll:3
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+
----------------
Do you need this?


================
Comment at: llvm/test/Transforms/InstCombine/mull.ll:5
+
+; Instcombine should be able to simplify mull operator.
+
----------------
Maybe rename this file mul-bool.ll ?


================
Comment at: llvm/test/Transforms/InstCombine/mull.ll:7
+
+define i64 @PR55599_One0(i64 %x, i64 %y) {
+; CHECK-LABEL: @PR55599_One0(
----------------
better descriptive test names - @test_mul_bit_x0_y0?

And add additional negativel test coverage such as 
```
define i64 @test_mul_bit_x0_y1(i64 %x, i64 %y) {
  %and1 = and i64 %x, 1
  %and2 = and i64 %y, 2
  %mul = mul i64 %and1, %and2
  ret i64 %mul
}
```

Vector tests as well would be good.


================
Comment at: llvm/test/Transforms/InstCombine/mull.ll:19
+
+define i64 @PR55599_One1(i64 %x, i64 %y, i64 %c) {
+; CHECK-LABEL: @PR55599_One1(
----------------
test_mul_bit_x0_yC


================
Comment at: llvm/test/Transforms/InstCombine/mull.ll:33
+; Aleady supported before
+define i64 @PR55599_Zero(i64 %x, i64 %y, i64 %c) {
+; CHECK-LABEL: @PR55599_Zero(
----------------
Isn't this covered by existing tests?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126040/new/

https://reviews.llvm.org/D126040