[PATCH] D126063: [AMDGPU] Add verification for mandatory literals

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
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Extend the literal operand checking in SIInstrInfo::verifyInstruction to
check VOP2 instructions like V_FMAAK_F32 which have a mandatory literal
operand. The rule is that src0 can also be a literal, but only if it is
the same literal value.

AMDGPUAsmParser::validateConstantBusLimitations already handles this
correctly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126063

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
  llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
  llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir


Index: llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
+++ llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
@@ -27,6 +27,15 @@
     $vgpr0 = V_FMA_F32_e64 0, $vgpr0, 0, 1077936128, 0, 1077936128, 0, 0, implicit $mode, implicit $exec
 ...
 
+---
+name: use_duplicate_literal_fmaak
+tracksRegLiveness: true
+body:            |
+  bb.0:
+    liveins: $vgpr0
+    $vgpr0 = V_FMAAK_F32 1077936128, $vgpr0, 1077936128, implicit $mode, implicit $exec
+...
+
 ---
 name: use_duplicate_literal_sop2
 tracksRegLiveness: true
Index: llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
+++ llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
@@ -16,6 +16,8 @@
 
 # GFX10PLUS-ERR: *** Bad machine code: VOP* instruction violates constant bus restriction ***
 # GFX10PLUS-ERR: $vgpr0 = V_CNDMASK_B32_e64 0, $sgpr0, 0, $sgpr2, killed $sgpr0_sgpr1, implicit $exec
+# GFX10PLUS-ERR: *** Bad machine code: VOP2/VOP3 instruction uses more than one literal ***
+# GFX10PLUS-ERR: $vgpr0 = V_FMAAK_F32 1077936128, $vgpr0, 0, implicit $mode, implicit $exec
 ---
 name:           sgpr_reuse_3sgpr
 liveins:
@@ -25,4 +27,5 @@
   bb.0:
     liveins: $sgpr0_sgpr1, $sgpr2
     $vgpr0 = V_CNDMASK_B32_e64 0, $sgpr0, 0, $sgpr2, killed $sgpr0_sgpr1, implicit $exec
+    $vgpr0 = V_FMAAK_F32 1077936128, $vgpr0, 0, implicit $mode, implicit $exec
 ...
Index: llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
+++ llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX10
+; RUN: not --crash llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s 2>&1 | FileCheck %s -check-prefix GFX10
 
 declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float)
 declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg)
@@ -6,7 +6,8 @@
 ; FIXME: This instruction uses two different literal constants which is not
 ; allowed.
 ; GFX10-LABEL: _amdgpu_ps_main:
-; GFX10: v_fmaak_f32 {{v[0-9]+}}, 0x40490fdb, {{v[0-9]+}}, 0xbfc90fdb
+; GFX10: Bad machine code: VOP2/VOP3 instruction uses more than one literal
+; GFX10: instruction: %4:vgpr_32 = nnan nsz arcp contract afn reassoc nofpexcept V_FMAAK_F32 1078530011, %0:vgpr_32, -1077342245, implicit $mode, implicit $exec
 define amdgpu_ps void @_amdgpu_ps_main(float %arg) {
 bb:
   %i = fmul reassoc nnan nsz arcp contract afn float %arg, 0x400921FB60000000
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4252,8 +4252,12 @@
     bool UsesLiteral = false;
     const MachineOperand *LiteralVal = nullptr;
 
-    if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1)
+    int ImmIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm);
+    if (ImmIdx != -1) {
       ++ConstantBusCount;
+      UsesLiteral = true;
+      LiteralVal = &MI.getOperand(ImmIdx);
+    }
 
     SmallVector<Register, 2> SGPRsUsed;
     Register SGPRUsed;
@@ -4280,8 +4284,8 @@
             UsesLiteral = true;
             LiteralVal = &MO;
           } else if (!MO.isIdenticalTo(*LiteralVal)) {
-            assert(isVOP3(MI));
-            ErrInfo = "VOP3 instruction uses more than one literal";
+            assert(isVOP2(MI) || isVOP3(MI));
+            ErrInfo = "VOP2/VOP3 instruction uses more than one literal";
             return false;
           }
         }


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