[llvm] dfe513a - Revert "[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates."

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-05-19T14:39:38-07:00
New Revision: dfe513ae1bb6e788ead93b850d80d77d54cf29d3

URL: https://github.com/llvm/llvm-project/commit/dfe513ae1bb6e788ead93b850d80d77d54cf29d3
DIFF: https://github.com/llvm/llvm-project/commit/dfe513ae1bb6e788ead93b850d80d77d54cf29d3.diff

LOG: Revert "[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates."

This reverts commit 86f7d7074a0129955aa2f5c82fe8c383eb17a35a.

The test cases added for this exposed an pre-existing bug that is failing
the expensive checks bot. Reverting so I can revert that patch.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/test/CodeGen/RISCV/rotl-rotr.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index a1e795819b1a8..b0e82e45e9ece 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -817,8 +817,8 @@ def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbbOrZbpOrZbkb]
 
 let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
-def : PatGprGpr<shiftop<rotl>, ROL>;
-def : PatGprGpr<shiftop<rotr>, ROR>;
+def : PatGprGpr<rotl, ROL>;
+def : PatGprGpr<rotr, ROR>;
 
 def : PatGprImm<rotr, RORI, uimmlog2xlen>;
 // There's no encoding for roli in the the 'B' extension as it can be
@@ -828,8 +828,8 @@ def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
 } // Predicates = [HasStdExtZbbOrZbpOrZbkb]
 
 let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
-def : PatGprGpr<shiftopw<riscv_rolw>, ROLW>;
-def : PatGprGpr<shiftopw<riscv_rorw>, RORW>;
+def : PatGprGpr<riscv_rolw, ROLW>;
+def : PatGprGpr<riscv_rorw, RORW>;
 def : PatGprImm<riscv_rorw, RORIW, uimm5>;
 def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
           (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;

diff  --git a/llvm/test/CodeGen/RISCV/rotl-rotr.ll b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
index 2026a756542ad..a7f7c38409a5f 100644
--- a/llvm/test/CodeGen/RISCV/rotl-rotr.ll
+++ b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
@@ -578,6 +578,7 @@ define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
 ;
 ; RV32ZBB-LABEL: rotl_32_mask_multiple:
 ; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andi a2, a2, 31
 ; RV32ZBB-NEXT:    rol a0, a0, a2
 ; RV32ZBB-NEXT:    rol a1, a1, a2
 ; RV32ZBB-NEXT:    add a0, a0, a1
@@ -585,6 +586,7 @@ define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
 ;
 ; RV64ZBB-LABEL: rotl_32_mask_multiple:
 ; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andi a2, a2, 31
 ; RV64ZBB-NEXT:    rolw a0, a0, a2
 ; RV64ZBB-NEXT:    rolw a1, a1, a2
 ; RV64ZBB-NEXT:    addw a0, a0, a1
@@ -702,6 +704,7 @@ define i64 @rotl_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {
 ;
 ; RV64ZBB-LABEL: rotl_64_mask_multiple:
 ; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andi a2, a2, 63
 ; RV64ZBB-NEXT:    rol a0, a0, a2
 ; RV64ZBB-NEXT:    rol a1, a1, a2
 ; RV64ZBB-NEXT:    add a0, a0, a1
@@ -741,6 +744,7 @@ define signext i32 @rotr_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
 ;
 ; RV32ZBB-LABEL: rotr_32_mask_multiple:
 ; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andi a2, a2, 31
 ; RV32ZBB-NEXT:    ror a0, a0, a2
 ; RV32ZBB-NEXT:    ror a1, a1, a2
 ; RV32ZBB-NEXT:    add a0, a0, a1
@@ -748,6 +752,7 @@ define signext i32 @rotr_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
 ;
 ; RV64ZBB-LABEL: rotr_32_mask_multiple:
 ; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andi a2, a2, 31
 ; RV64ZBB-NEXT:    rorw a0, a0, a2
 ; RV64ZBB-NEXT:    rorw a1, a1, a2
 ; RV64ZBB-NEXT:    addw a0, a0, a1
@@ -863,6 +868,7 @@ define i64 @rotr_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {
 ;
 ; RV64ZBB-LABEL: rotr_64_mask_multiple:
 ; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andi a2, a2, 63
 ; RV64ZBB-NEXT:    ror a0, a0, a2
 ; RV64ZBB-NEXT:    ror a1, a1, a2
 ; RV64ZBB-NEXT:    add a0, a0, a1