[PATCH] D125997: [AMDGPU] Instruction Type Pipeline

[Austin Kerbow via Phabricator via llvm-commits]

kerbowa added a comment.

Can you name these files something so that it is clear that it is a DAG mutation involving MFMA? I'm also not sure pipeline is the correct terminology here? I know that library folks have been calling it that.

Will we eventually be able to specify the order of the pipeline types and the size of each InstructionClass cluster?



================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUSchedPipeline.cpp:34
+
+static cl::opt<unsigned> PipelineStageMaxSize(
+    "amdgpu-pipeline-stage-size", cl::init(20), cl::Hidden,
----------------
This should be abstracted by instruction type.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUSchedPipeline.cpp:44
+  const IsInstructionType isInstructionClass;
+  const bool IsSized;
+
----------------
I'm not sure I understand what `IsSized` means?


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUSchedPipeline.cpp:51
+class SchedPipelineDAGMutation : public ScheduleDAGMutation {
+  //  const SIInstrInfo *TII;
+  //  ScheduleDAGMI *DAG;
----------------
Remove commented code.


Repository:
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  https://reviews.llvm.org/D125997/new/

https://reviews.llvm.org/D125997