[PATCH] D126009: [AMDGPU] Enforce alignment of image vaddr on gfx90a

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

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Even though single address image instructions only use a single VGPR
HW accesses 4 or 5 which creates alignment requirement.

Fixes: SWDEV-316648


https://reviews.llvm.org/D126009

Files:
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/MIMGInstructions.td
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
  llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
  llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir

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