[PATCH] D125997: Instruction Type Pipeline

[Jeffrey Byrnes via Phabricator via llvm-commits]

jrbyrnes created this revision.
jrbyrnes added reviewers: kerbowa, vangthao95, rampitec, arsenm.
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This patch implements a DAG mutation which adds edges between different groups of instructions. The purpose is to try to generate code that conforms to a pipeline (groupA instructions occur before groupB, groupB -> groupC, and so on). Currently the pipeline order is hardcoded as VMEM->DSRead->MFMA->DSWrite, but the patch was designed to be easily extensible. Alias analysis is problematic for pipelining as memory instructions will usually not be able to be reordered w.r.t one another.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125997

Files:
  llvm/lib/Target/AMDGPU/AMDGPUMFMAClustering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUMFMAClustering.h
  llvm/lib/Target/AMDGPU/AMDGPUSchedPipeline.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSchedPipeline.h
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/lib/Target/AMDGPU/CMakeLists.txt
  llvm/test/CodeGen/AMDGPU/mfma-cluster-edges.mir
  llvm/test/CodeGen/AMDGPU/mfma-cluster.mir
  llvm/test/CodeGen/AMDGPU/sched-pipeline-dag-mutation.mir

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