[llvm] d14f2a6 - [AMDGPU] Allow multiple uses of the same literal in SOP2/SOPC

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2022-05-19T16:42:20+01:00
New Revision: d14f2a6359483730657b275d40822d1098e3ff51

URL: https://github.com/llvm/llvm-project/commit/d14f2a6359483730657b275d40822d1098e3ff51
DIFF: https://github.com/llvm/llvm-project/commit/d14f2a6359483730657b275d40822d1098e3ff51.diff

LOG: [AMDGPU] Allow multiple uses of the same literal in SOP2/SOPC

AMDGPUAsmParser::validateSOPLiteral already knew about this but
SIInstrInfo::verifyInstruction did not.

Differential Revision: https://reviews.llvm.org/D125976

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 6d2ce9edb184a..cb1a4a269c946 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4366,16 +4366,11 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
   if (isSOP2(MI) || isSOPC(MI)) {
     const MachineOperand &Src0 = MI.getOperand(Src0Idx);
     const MachineOperand &Src1 = MI.getOperand(Src1Idx);
-    unsigned Immediates = 0;
 
-    if (!Src0.isReg() &&
-        !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
-      Immediates++;
-    if (!Src1.isReg() &&
-        !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
-      Immediates++;
-
-    if (Immediates > 1) {
+    if (!Src0.isReg() && !Src1.isReg() &&
+        !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType) &&
+        !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType) &&
+        !Src0.isIdenticalTo(Src1)) {
       ErrInfo = "SOP2/SOPC instruction requires too many immediate constants";
       return false;
     }

diff  --git a/llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir b/llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
index a6b6a01336d6e..a5920d3cac07c 100644
--- a/llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
+++ b/llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
@@ -26,3 +26,19 @@ body:            |
     ; CHECK: $vgpr0 = V_FMA_F32_e64 0, $vgpr0, 0, 1077936128, 0, 1077936128, 0, 0, implicit $mode, implicit $exec
     $vgpr0 = V_FMA_F32_e64 0, $vgpr0, 0, 1077936128, 0, 1077936128, 0, 0, implicit $mode, implicit $exec
 ...
+
+---
+name: use_duplicate_literal_sop2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    $sgpr0 = S_ADD_U32 12345, 12345, implicit-def $scc
+...
+
+---
+name: use_duplicate_literal_sopc
+tracksRegLiveness: true
+body: |
+  bb.0:
+    S_CMP_LG_U32 305419896, 305419896, implicit-def $scc
+...