[PATCH] D125962: [RISCV] Add a test showing overlapping stack offsets with RVV

[Fraser Cormack via Phabricator via llvm-commits]

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This test (and its forthcoming fix) was split off from D125787 <https://reviews.llvm.org/D125787>. It shows
that the logic we use to determine when we need to add extra RVV padding
is insufficient.

In this example, we may have a situation involving dynamic stack
alignment -- but no variable-sized objects -- where we have no FP but
must still use SP to index objects. In this case we also need the
extra RVV padding, otherwise objects may overlap. Specifically, the test
shows that the RVV vector object may clobber the lowest callee-save.

  |------------------------------| -- <-- Incoming SP
  | 4-byte callee-save (ra)      |
  |------------------------------| -- <-- SP + VLENB*2 + 60
  | 4-byte callee-save (s0)      |
  |------------------------------| -- <-- SP + VLENB*2 + 56  --
  | 4-byte callee-save (s9)      |                            |
  |------------------------------| -- <-- SP + VLENB*2 + 52   | RVV object(!!)
  | VLENB*2 RVV object           |                            |
  |------------------------------| -- <-- SP + 56            --
  | 4-byte local object          | 
  |------------------------------| -- <-- SP + 32
  | Dead area                    |
  |------------------------------| -- <-- InSP - 2*VLENB - 64
  | Possibly-zero realignment    | 
  |------------------------------| -- <-- SP (realigned to 32)

This diagram should help show that when SP==InSP -- e.g., when the incoming SP
is 32-byte aligned, subtracting 2*VLENB+64 may keep it that way -- the RVV
object clobbers the spill of s9.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125962

Files:
  llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir


Index: llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
+++ llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
@@ -2,7 +2,7 @@
 # RUN: llc -mtriple=riscv32 -mattr=+m,+v  -o - %s \
 # RUN:   -start-before=prologepilog | FileCheck %s
 #
-# This test checks that we are assigning the right stack slot to GPRs and to
+# These tests check that we are assigning the right stack slot to GPRs and to
 # vector registers (VRs). If this test changes, make sure there is no overlap
 # between slots for GPRs and VRs.
 --- |
@@ -27,6 +27,34 @@
     ret void
   }
 
+  ; FIXME: If the stack realignment does nothing to sp (a possibility) then
+  ; the vlenb*2-sized RVV stack object at sp+56 overlaps with the slot
+  ; allocated to spilling s9 (sp+52+vlenb*2)
+  define void @rvv_clobbers_callee_save() #0 {
+  ; CHECK-LABEL: rvv_clobbers_callee_save:
+  ; CHECK:       # %bb.0: # %entry
+  ; CHECK-NEXT:    addi sp, sp, -64
+  ; CHECK-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
+  ; CHECK-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
+  ; CHECK-NEXT:    sw s9, 52(sp) # 4-byte Folded Spill
+  ; CHECK-NEXT:    addi s0, sp, 64
+  ; CHECK-NEXT:    csrr a1, vlenb
+  ; CHECK-NEXT:    slli a1, a1, 1
+  ; CHECK-NEXT:    sub sp, sp, a1
+  ; CHECK-NEXT:    andi sp, sp, -32
+  ; CHECK-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
+  ; CHECK-NEXT:    addi a0, sp, 56
+  ; CHECK-NEXT:    vs2r.v v30, (a0) # Unknown-size Folded Spill
+  ; CHECK-NEXT:    addi sp, s0, -64
+  ; CHECK-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
+  ; CHECK-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
+  ; CHECK-NEXT:    lw s9, 52(sp) # 4-byte Folded Reload
+  ; CHECK-NEXT:    addi sp, sp, 64
+  ; CHECK-NEXT:    ret
+  entry:
+    ret void
+  }
+
   attributes #0 = { nounwind }
 ...
 ---
@@ -48,3 +76,22 @@
     PseudoRET
 
 ...
+---
+name:            rvv_clobbers_callee_save
+alignment:       2
+frameInfo:
+  maxAlignment:    8
+stack:
+  - { id: 0, type: spill-slot, size: 4, alignment: 32 }
+  - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector }
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $x10, $v30m2
+
+    $x25 = COPY $x10
+    SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0)
+    PseudoVSPILL_M2 renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8)
+    PseudoRET
+
+...


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