[PATCH] D125956: [NOT YET FOR REVIEW][AArch64][LV] Implement AArch64TTIImpl::getRegisterClassForType
Peter Waller via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 19 02:36:31 PDT 2022
peterwaller-arm created this revision.
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NOTE: I'm sending this for early review. Here's a possible solution to fixing
the register class issue, if it needs fixing. Another solution would be to have
`getRegUsageForType` return a tuple of (Count, Class), but this might not be
straightforward to implement for all targets, I haven't investigated.
The loop vectorizer uses `getRegisterClassForType` to determine the
register class occupied by a given an `llvm::Type*` for the purposes of
register pressure estimation, which in turn feeds into the choice of the
a maximum VF to use.
As part of this, the loop vectorizer has a heuristic
`isScalarAfterVectorization`, which `getRegisterClassForType(bool
Vector, Type *Ty)` effectively receives as its 'Vector' parameter. The
default implementation of `getRegisterClassForType` ignores the `Type`
parameter, just returning a 'VectorRC' if Vector is True.
However, some large vector types (e.g. v128i1) are represented with a
number of scalar registers. This is known by `TLI->getRegisterType`, so
add a `TTI` interface `getRegMVTForType` and propagate this information
up to the newly implemented `getRegisterClassForType`.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D125956
Files:
llvm/include/llvm/Analysis/TargetTransformInfo.h
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/include/llvm/CodeGen/BasicTTIImpl.h
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
llvm/test/Transforms/LoopVectorize/AArch64/i1-reg-usage.ll
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