[PATCH] D125546: [RISCV] Use tail agnostic if inserting subvector/element at the end of the vector.

Roger Ferrer Ibanez via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu May 19 00:17:28 PDT 2022


rogfer01 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4429
+  int PolicyVal = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
+  // We could use tail agnostic if it's inserting to the latest of a vector.
+  if (VecVT.isFixedLengthVector() && isa<ConstantSDNode>(Idx) &&
----------------
I'd use "at the end of the vector" (I think "latest" is about time)


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5360
+    if (VecVT.isFixedLengthVector() &&
+        (OrigIdx + SubVecVT.getVectorNumElements() + 1) ==
+            VecVT.getVectorNumElements())
----------------
I'm a bit confused here, probably I misunderstood what we mean by the end of the vector.

In the following testcase taken from `fixed-vectors-fp-shuffles.ll`


```lang=llvm
define void @insert_v32i1_v8i1_16(<32 x i1>* %vp, <8 x i1>* %svp) #0 {
  %v = load <32 x i1>, <32 x i1>* %vp, align 4
  %sv = load <8 x i1>, <8 x i1>* %svp, align 1
  %c = call <32 x i1> @llvm.experimental.vector.insert.v32i1.v8i1(<32 x i1> %v, <8 x i1> %sv, i64 16)
  store <32 x i1> %c, <32 x i1>* %vp, align 4
  ret void
}

declare <32 x i1> @llvm.experimental.vector.insert.v32i1.v8i1(<32 x i1> %v, <8 x i1> %sv, i64 %idx)
```

Once the mask types are promoted to integer types we have: `OrigIdx == 2`, `VecVT == v4i8`, and `SubVecVT == v1i8`. My impression is that the end of the vector in this case would be when `OrigIdx == 3`. Does this align with your expectation or my notion of "end" is incorrect?

The condition check does `2 + 1 + 1 == 4` so we make this tail agnostic. Perhaps, not sure, the last `+ 1` is not needed (it was needed for the insert element case because you were checking the index in the vector).


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:1843
 
-def SDTRVVSlide : SDTypeProfile<1, 5, [
+// We use vsludeup with different tail policy to implement insert subvector or
+// element operations.
----------------
Typo `vslideup`


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