[PATCH] D125335: Give option to use isCopyInstr to determine which MI is treated as Copy instruction in MCP

[Xin Tong via Phabricator via llvm-commits]

adriantong1024 added a comment.

In D125335#3522676 <https://reviews.llvm.org/D125335#3522676>, @arsenm wrote:

> Can you avoid adding a second run by moving the current run? The ad-hoc physreg liveness tracking after allocation is really expensive

Hi @arsenm

Thanks for the review. I tried to move the current pass after machine block placement. The problem with this is machine block placement runs after Post-RA pseudo instruction expansion pass and postrapseudos changes COPY instruction to real instructions, MCP cant handle real instructions with MI.isCopy(). e.g. test/CodeGen/ARM/sadd_sat_plus.ll.

Before postrapseudos
bb.4 (%ir-block.0):
liveins: $r0, $r3
renamable $r2 = COPY killed renamable $r3
$r1 = COPY killed renamable $r2
tPOP_RET 14, $noreg, def $r4, def $pc, implicit-def $sp, implicit $sp, implicit $r0, implicit $r1

After postrapseudos
bb.4 (%ir-block.0):
liveins: $r0, $r3
$r2 = tMOVr killed $r3, 14, $noreg
$r1 = tMOVr killed $r2, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $pc, implicit-def $sp, implicit $sp, implicit $r0, implicit $r1

After MCP
bb.4 (%ir-block.0):
liveins: $r0, $r3
$r2 = tMOVr killed $r3, 14, $noreg
$r1 = tMOVr killed $r2, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $pc, implicit-def $sp, implicit $sp, implicit $r0, implicit $r1

Right now this additional pass only happens on AArch64 and its removing things that could not be done with the first pass of MCP.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D125335/new/

https://reviews.llvm.org/D125335