[PATCH] D125900: [AMDGPU][NFC] Fix FileCheck directives in phi-vgpr-input-moveimm.mir.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev created this revision.
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Discovered with D125604 <https://reviews.llvm.org/D125604>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125900

Files:
  llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir


Index: llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
+++ llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
@@ -1,6 +1,6 @@
 # RUN: llc  -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
 ---
-# GCN_LABEL: phi_moveimm_input
+# GCN-LABEL: name: phi_moveimm_input
 # GCN-NOT: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
 # GCN:     %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
 
@@ -33,7 +33,7 @@
 ...
 
 ---
-# GCN_LABEL: phi_moveimm_subreg_input
+# GCN-LABEL: name: phi_moveimm_subreg_input
 # GCN-NOT: %{{[0-9]+}}:sreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
 # GCN: %{{[0-9]+}}:vreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
 name:            phi_moveimm_subreg_input
@@ -66,7 +66,7 @@
 
 
 ---
-# GCN_LABEL: phi_moveimm_bad_opcode_input
+# GCN-LABEL: name: phi_moveimm_bad_opcode_input
 # GCN-NOT: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
 # GCN: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
 name:            phi_moveimm_bad_opcode_input


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