[PATCH] D116088: [compiler-rt] Implement ARM atomic operations for architectures without SMP support

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

On a target that doesn't support SMP, you don't need memory barriers, sure.  (I think we'd want a CMake flag to explicitly assert that you're only going to run the code on chips without SMP.)

That doesn't really solve your issue, though.  To implement atomic compare-and-swap or rmw operations, you need to ensure your code doesn't get interrupted in the middle.  If your system supports multithreading, and a thread can be preempted at any time, you need one of the following:

1. A natively atomic operation, like strex.
2. A way to temporarily turn off interrupts, so the thread can't be preempted for a short time.
3. Kernel-assisted operations, like the Linux kernel provides.
4. A separate lock.

None of these options work on armv5 without some sort of kernel assistance.  (Well, technically, you can implement a spinlock with swp, but that's very inefficient.)


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https://reviews.llvm.org/D116088