[PATCH] D125700: [AMDGPU][GFX9] Support base+soffset+offset SMEM loads.

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SMInstructions.td:544
+  // documentation suggesting otherwise.
+  // TODO: Ignore soffset_en when disassembling GFX8 instructions.
+  let Inst{14} = !if(ps.has_offset, ps.has_soffset, !if(ps.has_soffset, 0, ?));
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kosarev wrote:
> dp wrote:
> > kosarev wrote:
> > > dp wrote:
> > > > kosarev wrote:
> > > > > Would love some opinions on how important we think it would be to support that. If I don't miss anything, addressing this would mean either further customising `AMDGPUDisassembler::getInstruction()` or split the TableGen definitions for GFX8 and GFX9 -- and not just the SMEM ones. Which seems to be a significant amount of changes.
> > > > >// TODO: Ignore soffset_en when disassembling GFX8 instructions.
> > > > Are there cases when an illegal GFX8 code may be decoded with soffset_en=1? The _SGPR_IMM_vi case should not work for GFX8, should it?
> > > Not sure I read the question right, but I understand, e.g., `0xc0024141 0x00012345` (with imm=1 and soffset_en=1) should decode to `s_load_dword s5, s[2:3], s0 offset:0x12345` in GFX9 and to `s_load_dword s5, s[2:3], 0x12345` in GFX8. With this patch in place we fail to do the latter because our GFX8 and GFX9 definitions share the same decoding namespace; the `isGFX9Only` predicate for the `_SGPR_IMM` case below makes it non-instruction in GFX8.
> > So after this change disassembler will be unable to decode some legal GFX8 code, correct? I think this should be avoided. Would it be difficult to amend this patch with disassembler changes to avoid this breakage?
> As there is no `soffset_en` in GFX8, all codes with that bit raised are not what I guess you call legal GFX8 codes. I think we would never normally produce such codes for GFX8 from codegen or assembly, but as of the moment I'm not aware of any reasons to think that such codes are actually illegal or invalid. That is basically a disassembling issue again.
You are right, this is a corner case which does not look that important. However there are third-party tools which may produce such codes, you never know. We should be able to disassemble such codes unless this requires a lot of additional work.


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Comment at: llvm/test/MC/AMDGPU/gfx9_asm_smem.s:63
 
+s_load_dword s5, s[2:3], s0 offset:0x12345
+// CHECK: [0x41,0x41,0x02,0xc0,0x45,0x23,0x01,0x00]
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kosarev wrote:
> dp wrote:
> > kosarev wrote:
> > > dp wrote:
> > > > It is a minor issue, but I noted that all your new tests use soffset=s0. It may be a good idea to avoid operands which are encoded as 0 (or add tests with other operands as well).
> > > Agree, and so seem to do the other tests here. I don't mind to update them all, if that's the suggestion?
> > The file has tests with s101, m0, etc for soffset so the coverage is sufficient. I suggest to correct one new test to use e.g. s1 instead of s0.
> Done.
> 
> Note that there are still lots of other MC tests and test cases where only s0 is used at a register position. And then on a more general note, I admit I struggle a bit to see the point in testing all possible combinations of what encoding-, diagnostics- and implementation-wise seems to be completely unrelated, such as immediate/register operands and glc modifiers, if that's the right example. Feels like removing unnecessary repetitions would make uncovered cases more visible, allow more combinations that we are truly interested in and maybe somewhat reduce testing times.
The tests in this file have been generated by a script with the purpose of black box testing. The script did not generate all combinations of operands and modifiers, it attempted to provide at least one test for each operand kind and each modifier value. And yes, these tests are not perfect.

When working on a feature you do not have to mimic generated tests. Add a minimal set of tests which you feel would be sufficient for good coverage. 


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  https://reviews.llvm.org/D125700/new/

https://reviews.llvm.org/D125700