[PATCH] D125865: [AArch64] Fix zero element TBL indices

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 18 02:43:36 PDT 2022


dmgreen created this revision.
dmgreen added reviewers: samtebbs, SjoerdMeijer, jaykang10, fhahn, sdesmalen.
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A TBL instruction will fill out-of-range values with 0's, something used in D121139 <https://reviews.llvm.org/D121139> to turn tbl2 with a zero input into tbl1s. This works OK for v16i8, but for v8i8 the input is still treated as a v16i8, so "out-of-range" values (like a lane index of 8) would end up loading values from the top half of the input register. Clean this up by detecting the out of range values and making sure they really use out of range values. There is a fix for swapped indices of 64bit input vectors too, which could be incorrectly adjusted if the zerovector was the first operand.

Fixes #55545


https://reviews.llvm.org/D125865

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll

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