[PATCH] D125310: [AArch64][RISCV][SelectionDAG] Support VECREDUCE_ADD mask operations

WangLian via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 17 23:53:28 PDT 2022


Jimerlife added a comment.

In D125310#3517804 <https://reviews.llvm.org/D125310#3517804>, @Jimerlife wrote:

> In D125310#3515962 <https://reviews.llvm.org/D125310#3515962>, @reames wrote:
>
>> Please go ahead and land the new tests, and then rebase so that changes in codegen are visible in review.  Also, please rebase over the mentioned Aarch64 review.  The test diff there currently looks like a regression because you haven't stacked the changes which was confusing at first.
>>
>> The submission comment needs improved to describe what this is actually doing.
>>
>> The patch seems generally reasonable.  Once the above are done, should be an easy LGTM.
>
> Thanks for your advice. After I rebased main, this patch no longer affect AArch64 tests.

I misunderstood what you meant before.In RISCV, VECREDUCE_ADD mask operations is unsupport, so I cann't precommit  scalable vector tests. Before D125605 <https://reviews.llvm.org/D125605> landed, my patch affect a AArch64 test(`vecreduce-add-legalization.ll`), but now this is no affect after D125605 <https://reviews.llvm.org/D125605> landed.


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