[PATCH] D125747: [RISCV] Enable scalable vectorization by default for RVV

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead added inline comments.


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/unroll-in-loop-vectorizer.ll:48
+; CHECK-NEXT:    [[TMP25:%.*]] = bitcast i32* [[TMP24]] to <vscale x 2 x i32>*
+; CHECK-NEXT:    store <vscale x 2 x i32> [[TMP20]], <vscale x 2 x i32>* [[TMP25]], align 4
+; CHECK-NEXT:    [[TMP26:%.*]] = call i32 @llvm.vscale.i32()
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craig.topper wrote:
> pcwang-thead wrote:
> > For example, I believe this `store` is unnecessary.
> Why is it unnecessary? I think the loop is processing using two vector loads/store due to RISCVSubtarget::getMaxInterleaveFactor()
Oops, you're right.
I think the problem is that we are using RVV as SIMD now, so we will:
* read vlenb to calculate vector length.
* use `vsetvli _, zero, ...` to set vl/vtype and ignore returned vl. This is inserted by InsertVSETVLI pass.
* handle tail in scalar loop (may have been improved in D121595?).



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