[PATCH] D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes.

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM



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Comment at: llvm/test/CodeGen/RISCV/pass-fast-math-flags-sdnode.ll:1
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -debug-only=isel -o /dev/null 2>&1                        | FileCheck %s
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fakepaper56 wrote:
> fakepaper56 wrote:
> > craig.topper wrote:
> > > I didn't think about this before, but is it possible to use -stop-after=finalize-isel and inspect the MIR output instead? That wouldn't require an asserts build.
> > There is no optimization of VP using fast math flags and I don't know how to make MIR print fast-math flags. The output of `llc -mtriple=riscv64 -mattr=+v fa. -stop-after=finalize-isel` : 
> > `%7:vrnov0 = nofpexcept PseudoVFMUL_VV_M1_MASK %8, %0, %1, $v0, killed %6, 6 /* e64 */, 1, implicit $frm`
> Could we get MIR
I think we're dropping the fast math flags when we go from ISD::VP* to RISCVISD::*_VL. So my suggestion won't work without a lot more work.

We can use the debug output and `REQUIRES: asserts`


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https://reviews.llvm.org/D125600