[PATCH] D125747: [RISCV] Enable scalable vectorization by default for RVV

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead added a comment.

I have done some researches before, the quality of vectorized code haven't met our expectation currently.
Actually, it is just SIMD-style vectorization for RVV for the time being.
Maybe we should wait VP-based vectorization?



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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/unroll-in-loop-vectorizer.ll:48
+; CHECK-NEXT:    [[TMP25:%.*]] = bitcast i32* [[TMP24]] to <vscale x 2 x i32>*
+; CHECK-NEXT:    store <vscale x 2 x i32> [[TMP20]], <vscale x 2 x i32>* [[TMP25]], align 4
+; CHECK-NEXT:    [[TMP26:%.*]] = call i32 @llvm.vscale.i32()
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For example, I believe this `store` is unnecessary.


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  https://reviews.llvm.org/D125747/new/

https://reviews.llvm.org/D125747