[PATCH] D125700: [AMDGPU][GFX9] Support base+soffset+offset SMEM loads.

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SMInstructions.td:544
+  // documentation suggesting otherwise.
+  // TODO: Ignore soffset_en when disassembling GFX8 instructions.
+  let Inst{14} = !if(ps.has_offset, ps.has_soffset, !if(ps.has_soffset, 0, ?));
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kosarev wrote:
> dp wrote:
> > kosarev wrote:
> > > Would love some opinions on how important we think it would be to support that. If I don't miss anything, addressing this would mean either further customising `AMDGPUDisassembler::getInstruction()` or split the TableGen definitions for GFX8 and GFX9 -- and not just the SMEM ones. Which seems to be a significant amount of changes.
> > >// TODO: Ignore soffset_en when disassembling GFX8 instructions.
> > Are there cases when an illegal GFX8 code may be decoded with soffset_en=1? The _SGPR_IMM_vi case should not work for GFX8, should it?
> Not sure I read the question right, but I understand, e.g., `0xc0024141 0x00012345` (with imm=1 and soffset_en=1) should decode to `s_load_dword s5, s[2:3], s0 offset:0x12345` in GFX9 and to `s_load_dword s5, s[2:3], 0x12345` in GFX8. With this patch in place we fail to do the latter because our GFX8 and GFX9 definitions share the same decoding namespace; the `isGFX9Only` predicate for the `_SGPR_IMM` case below makes it non-instruction in GFX8.
So after this change disassembler will be unable to decode some legal GFX8 code, correct? I think this should be avoided. Would it be difficult to amend this patch with disassembler changes to avoid this breakage?


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Comment at: llvm/lib/Target/AMDGPU/SMInstructions.td:559
+  // (no-offset + soffset) case, namely:
+  //   imm=0  soffset_en=1  offset=?  soffset=<soffset>
+  //   imm=1  soffset_en=1  offset=0  soffset=<soffset>
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kosarev wrote:
> dp wrote:
> > This addressing mode is semantically equivalent to the one where soffset is encoded in the offset field. I'm not sure we really need it. Note that sp3 has no syntactic sugar to enforce this encoding. It may be useful for decoder, but I doubt it worth the trouble.
> Yes, these are not needed for codegen needs and may only be useful for disassembling. Should we leave the TODOs be until we know for sure what to do with this?
Let us see what other people here think. I'd have replaced TODOs with a description of limitations of the current design. But this is a matter of taste.


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Comment at: llvm/test/MC/AMDGPU/gfx9_asm_smem.s:63
 
+s_load_dword s5, s[2:3], s0 offset:0x12345
+// CHECK: [0x41,0x41,0x02,0xc0,0x45,0x23,0x01,0x00]
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kosarev wrote:
> dp wrote:
> > It is a minor issue, but I noted that all your new tests use soffset=s0. It may be a good idea to avoid operands which are encoded as 0 (or add tests with other operands as well).
> Agree, and so seem to do the other tests here. I don't mind to update them all, if that's the suggestion?
The file has tests with s101, m0, etc for soffset so the coverage is sufficient. I suggest to correct one new test to use e.g. s1 instead of s0.


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  https://reviews.llvm.org/D125700/new/

https://reviews.llvm.org/D125700