[PATCH] D125700: [AMDGPU][GFX9] Support base+soffset+offset SMEM loads.

Tue May 17 06:21:14 PDT 2022

arsenm added inline comments.

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Comment at: llvm/test/MC/AMDGPU/gfx9_asm_smem.s:126

+s_load_dwordx2 s[10:11], s[2:3], s0 offset:0x12345
+// CHECK: [0x81,0x42,0x06,0xc0,0x45,0x23,0x01,0x00]
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kosarev wrote:
> rampitec wrote:
> > kosarev wrote:
> > > arsenm wrote:
> > > > An unaligned offset is suspicious looking but technically not wrong
> > > I assume we are only interested in how instructions are getting encoded here, so no need for them to look very realistic?
> > Isn't the final address has to be aligned, not partial offsets? I.e. this shall be fine even if we wanted to enforce something in the asm.
> Yes, my understanding is that it's only the resulting address that has to be aligned.
Yes, the final address is all that matters. But practically speaking that always means a well aligned offset (still not sure why they switched this to a byte offset)

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125700/new/

https://reviews.llvm.org/D125700