[PATCH] D125607: [DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D125607#3518372 <https://reviews.llvm.org/D125607#3518372>, @dmgreen wrote:

> Do you know what makes the AArch64::shouldFoldConstantShiftPairToMask necessary? Is it just something about those tests, or something fundamental to the architecture?

There were a number of test regressions - some of the UXTB matching is affected again (I think this was mainly in a followup patch that I'm working on for an equivalent (srl (shl x, c1), c2)) fold) and some load multiple / calling convention tests were messed up.

Shall I update the patch showing the regressions for comparison?

I'd be happy to address these in a followup patch which will relax/remove the AArch64TargetLowering::shouldFoldConstantShiftPairToMask limit again - I'm currently thinking/hoping using this callback in ARM/AArch64 will help with the UXTB regressions I keep hitting.


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https://reviews.llvm.org/D125607