[PATCH] D125713: [WebAssembly][NFC] Convert StackBased instruction field to 'bit' from string

[Alex Bradbury via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG601ed0b60531: [WebAssembly][NFC] Convert StackBased instruction field to 'bit' from string (authored by asb).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125713/new/

https://reviews.llvm.org/D125713

Files:
  llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
  llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp


Index: llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
===================================================================
--- llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
+++ llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
@@ -55,11 +55,7 @@
     auto &CGIP = OpcodeTable[Prefix][Opc];
     // All wasm instructions have a StackBased field of type string, we only
     // want the instructions for which this is "true".
-    auto StackString =
-        Def.getValue("StackBased")->getValue()->getCastTo(StringRecTy::get(RK));
-    auto IsStackBased =
-        StackString &&
-        reinterpret_cast<const StringInit *>(StackString)->getValue() == "true";
+    bool IsStackBased = Def.getValueAsBit("StackBased");
     if (!IsStackBased)
       continue;
     if (CGIP.second) {
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
===================================================================
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
@@ -225,8 +225,8 @@
   let FilterClass = "StackRel";
   let RowFields = ["BaseName"];
   let ColFields = ["StackBased"];
-  let KeyCol = ["false"];
-  let ValueCols = [["true"]];
+  let KeyCol = ["0"];
+  let ValueCols = [["1"]];
 }
 
 //===----------------------------------------------------------------------===//
@@ -238,8 +238,8 @@
   let FilterClass = "RegisterRel";
   let RowFields = ["BaseName"];
   let ColFields = ["StackBased"];
-  let KeyCol = ["true"];
-  let ValueCols = [["false"]];
+  let KeyCol = ["1"];
+  let ValueCols = [["0"]];
 }
 
 //===----------------------------------------------------------------------===//
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
===================================================================
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
@@ -14,10 +14,10 @@
 // WebAssembly Instruction Format.
 // We instantiate 2 of these for every actual instruction (register based
 // and stack based), see below.
-class WebAssemblyInst<bits<32> inst, string asmstr, string stack, string is64>
+class WebAssemblyInst<bits<32> inst, string asmstr, bit stack, string is64>
   : StackRel, RegisterRel, Wasm64Rel, Instruction {
   bits<32> Inst = inst; // Instruction encoding.
-  string StackBased = stack;
+  bit StackBased = stack;
   string BaseName = NAME;
   string IsWasm64 = is64;
   string Wasm32Name = !subst("_A64", "_A32", NAME);
@@ -30,7 +30,7 @@
 }
 
 // Normal instructions. Default instantiation of a WebAssemblyInst.
-class NI<dag oops, dag iops, list<dag> pattern, string stack,
+class NI<dag oops, dag iops, list<dag> pattern, bit stack,
          string asmstr = "", bits<32> inst = -1, string is64 = "false">
     : WebAssemblyInst<inst, asmstr, stack, is64> {
   dag OutOperandList = oops;
@@ -56,9 +56,9 @@
              list<dag> pattern_r, string asmstr_r = "", string asmstr_s = "",
              bits<32> inst = -1, string is64 = "false"> {
   let isCodeGenOnly = 1 in
-  def "" : NI<oops_r, iops_r, pattern_r, "false", asmstr_r, inst, is64>;
+  def "" : NI<oops_r, iops_r, pattern_r, false, asmstr_r, inst, is64>;
   let BaseName = NAME in
-  def _S : NI<oops_s, iops_s, [], "true", asmstr_s, inst, is64>;
+  def _S : NI<oops_s, iops_s, [], true, asmstr_s, inst, is64>;
 }
 
 // For instructions that have no register ops, so both sets are the same.


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