[PATCH] D125607: [DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 17 02:38:00 PDT 2022

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RKSimon added a comment.

@foad @dmgreen Any objections to the AMDGPU / ARM changes?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125607/new/

https://reviews.llvm.org/D125607

Previous message: [PATCH] D124526: [SimpleLoopUnswitch] Collect either logical ANDs/ORs but not both.
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