[llvm] 05ad4d4 - [RISCV][NFC] Fix comment typos in split SP adjustment

[Fraser Cormack via llvm-commits]

Author: Fraser Cormack
Date: 2022-05-17T09:56:54+01:00
New Revision: 05ad4d4f38689114a54f79fdd07d18552ee902e2

URL: https://github.com/llvm/llvm-project/commit/05ad4d4f38689114a54f79fdd07d18552ee902e2
DIFF: https://github.com/llvm/llvm-project/commit/05ad4d4f38689114a54f79fdd07d18552ee902e2.diff

LOG: [RISCV][NFC] Fix comment typos in split SP adjustment

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index e71de3e32981e..fe642bab208bd 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1034,9 +1034,9 @@ RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const {
   // Return the FirstSPAdjustAmount if the StackSize can not fit in signed
   // 12-bit and there exists a callee saved register need to be pushed.
   if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
-    // FirstSPAdjustAmount is choosed as (2048 - StackAlign)
+    // FirstSPAdjustAmount is chosen as (2048 - StackAlign)
     // because 2048 will cause sp = sp + 2048 in epilogue split into
-    // multi-instructions. The offset smaller than 2048 can fit in signle
+    // multi-instructions. The offset smaller than 2048 can fit in single
     // load/store instruction and we have to stick with the stack alignment.
     // 2048 is 16-byte alignment. The stack alignment for RV32 and RV64 is 16,
     // for RV32E is 4. So (2048 - StackAlign) will satisfy the stack alignment.