[PATCH] D125446: [LegalizeVectorTypes][VP] Add widen and split support for VP_SETCC

[WangLian via Phabricator via llvm-commits]

Jimerlife added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:2119
+  assert(N->getNumOperands() == 5 && "Unexpected number of operands!");
+  assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
+
----------------
craig.topper wrote:
> This assert provides no value. It's the oppose of the `if` you wrote above.
Now, I used if and else instead.Thanks.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3504
+
+  if (N->getOpcode() == ISD::VP_SETCC) {
+    SDValue MaskLo, MaskHi, EVLLo, EVLHi;
----------------
craig.topper wrote:
> Use an `else` with an `assert(N->getOpcode() == ISD::VP_SETCC)` inside
Done. Use an else instead.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125446/new/

https://reviews.llvm.org/D125446