[PATCH] D125737: [AArch64] Use ADDV for boolean xor reductions.

[Ruobing Han via Phabricator via llvm-commits]

drcut created this revision.
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NEON does not have native support for xor reductions. However, when
reducing predicate vectors the operation is synonymous with an add
reduction that is supported.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125737

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/reduce-xor.ll

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