[PATCH] D125703: [RISCV] Fix missing vsetvli in transparent block case

Mon May 16 13:36:11 PDT 2022

reames added inline comments.

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Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll:30
 ; CHECK-NEXT:    vfadd.vv v8, v8, v9
+; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
 ; CHECK-NEXT:    ret
----------------
reames wrote:
> craig.topper wrote:
> > Does this mean that ExitInfo and CurInfo don't match at the end? Why did that occur? There's nothing that has any special cases in this function.
> > 
> > Is it because of the AVL being from a vsetvli?
> It's because the AVL on the abstract state is technically not equal.  They both represent the same runtime value, but the first state has an AVL of a0, the vfsub produces one with an AVL of x0 (vlmax).  This is due to my recently introduce prepass which creates this canonicalization.
> 
> We could pretty easily fix this with a minor improvement to insertVSETVLI, but given the following patch immediately reverses this, I left it to avoid complicating the patch series further.  :)
Slight correction here.  The final state after the vfsub has an AVL produced by the first instruction (not vlmax as I said before.)  The difference between stage 1/2 and 3 is that having the prior state lets us realize that is compatible (e.g. same bits in registers).  We then emit the end of block check to bring the abstract state back in sync.

This hints we could reuse needVSETVLI in the compensation check, but since the compensation code is about to disappear, I don't know this is worth doing.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125703/new/

https://reviews.llvm.org/D125703