[PATCH] D125601: [DAGCombiner][AArch64] Reorder the bitcast of scalable vector

[Allen zhong via Phabricator via llvm-commits]

Allen updated this revision to Diff 429726.
Allen added a comment.

update review
1、add restrict for index ==0 and legal for types
2、move test into file llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125601/new/

https://reviews.llvm.org/D125601

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll

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