[llvm] 7272a8c - [AArch64] Update check lines in arm64-scvt.ll. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon May 16 07:50:45 PDT 2022
Author: David Green
Date: 2022-05-16T15:50:39+01:00
New Revision: 7272a8c23ceb218b3bd6f0dd303c6df2c773cc74
URL: https://github.com/llvm/llvm-project/commit/7272a8c23ceb218b3bd6f0dd303c6df2c773cc74
DIFF: https://github.com/llvm/llvm-project/commit/7272a8c23ceb218b3bd6f0dd303c6df2c773cc74.diff
LOG: [AArch64] Update check lines in arm64-scvt.ll. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-scvt.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-scvt.ll b/llvm/test/CodeGen/AArch64/arm64-scvt.ll
index d886d7cd846d..069f33daaad7 100644
--- a/llvm/test/CodeGen/AArch64/arm64-scvt.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-scvt.ll
@@ -1,42 +1,50 @@
-; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck -enable-var-scope %s
-; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cortex-a57 | FileCheck -enable-var-scope --check-prefix=CHECK-A57 %s
-; rdar://13082402
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck --check-prefixes=CHECK,CHECK-CYC %s
+; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cortex-a57 | FileCheck --check-prefixes=CHECK,CHECK-A57 %s
define float @t1(i32* nocapture %src) nounwind ssp {
-entry:
; CHECK-LABEL: t1:
-; CHECK: ldr s0, [x0]
-; CHECK: scvtf s0, s0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0]
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: ret
+entry:
%tmp1 = load i32, i32* %src, align 4
%tmp2 = sitofp i32 %tmp1 to float
ret float %tmp2
}
define float @t2(i32* nocapture %src) nounwind ssp {
-entry:
; CHECK-LABEL: t2:
-; CHECK: ldr s0, [x0]
-; CHECK: ucvtf s0, s0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: ret
+entry:
%tmp1 = load i32, i32* %src, align 4
%tmp2 = uitofp i32 %tmp1 to float
ret float %tmp2
}
define double @t3(i64* nocapture %src) nounwind ssp {
-entry:
; CHECK-LABEL: t3:
-; CHECK: ldr d0, [x0]
-; CHECK: scvtf d0, d0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: scvtf d0, d0
+; CHECK-NEXT: ret
+entry:
%tmp1 = load i64, i64* %src, align 4
%tmp2 = sitofp i64 %tmp1 to double
ret double %tmp2
}
define double @t4(i64* nocapture %src) nounwind ssp {
-entry:
; CHECK-LABEL: t4:
-; CHECK: ldr d0, [x0]
-; CHECK: ucvtf d0, d0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: ret
+entry:
%tmp1 = load i64, i64* %src, align 4
%tmp2 = uitofp i64 %tmp1 to double
ret double %tmp2
@@ -44,10 +52,12 @@ entry:
; rdar://13136456
define double @t5(i32* nocapture %src) nounwind ssp optsize {
-entry:
; CHECK-LABEL: t5:
-; CHECK: ldr [[REG:w[0-9]+]], [x0]
-; CHECK: scvtf d0, [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: scvtf d0, w8
+; CHECK-NEXT: ret
+entry:
%tmp1 = load i32, i32* %src, align 4
%tmp2 = sitofp i32 %tmp1 to double
ret double %tmp2
@@ -71,9 +81,11 @@ entry:
; ********* 1. load with scaled imm to float. *********
define float @fct1(i8* nocapture %sp0) {
; CHECK-LABEL: fct1:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr b0, [x0, #1]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 1
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@@ -84,9 +96,11 @@ entry:
define float @fct2(i16* nocapture %sp0) {
; CHECK-LABEL: fct2:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr h0, [x0, #2]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 1
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@@ -97,9 +111,11 @@ entry:
define float @fct3(i32* nocapture %sp0) {
; CHECK-LABEL: fct3:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0, #4]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 1
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@@ -111,9 +127,11 @@ entry:
; i64 -> f32 is not supported on floating point unit.
define float @fct4(i64* nocapture %sp0) {
; CHECK-LABEL: fct4:
-; CHECK: ldr x[[REGNUM:[0-9]+]], [x0, #8]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr x8, [x0, #8]
+; CHECK-NEXT: ucvtf s0, x8
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 1
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@@ -125,9 +143,11 @@ entry:
; ********* 2. load with scaled register to float. *********
define float @fct5(i8* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct5:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr b0, [x0, x1]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 %offset
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@@ -138,9 +158,11 @@ entry:
define float @fct6(i16* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct6:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr h0, [x0, x1, lsl #1]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 %offset
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@@ -151,9 +173,11 @@ entry:
define float @fct7(i32* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct7:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0, x1, lsl #2]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 %offset
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@@ -165,9 +189,11 @@ entry:
; i64 -> f32 is not supported on floating point unit.
define float @fct8(i64* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct8:
-; CHECK: ldr x[[REGNUM:[0-9]+]], [x0, x1, lsl #3]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr x8, [x0, x1, lsl #3]
+; CHECK-NEXT: ucvtf s0, x8
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 %offset
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@@ -180,9 +206,11 @@ entry:
; ********* 3. load with scaled imm to double. *********
define double @fct9(i8* nocapture %sp0) {
; CHECK-LABEL: fct9:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr b0, [x0, #1]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 1
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@@ -193,9 +221,11 @@ entry:
define double @fct10(i16* nocapture %sp0) {
; CHECK-LABEL: fct10:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr h0, [x0, #2]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 1
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@@ -206,9 +236,11 @@ entry:
define double @fct11(i32* nocapture %sp0) {
; CHECK-LABEL: fct11:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0, #4]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 1
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@@ -219,9 +251,11 @@ entry:
define double @fct12(i64* nocapture %sp0) {
; CHECK-LABEL: fct12:
-; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, #8]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr d0, [x0, #8]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 1
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@@ -233,9 +267,11 @@ entry:
; ********* 4. load with scaled register to double. *********
define double @fct13(i8* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct13:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr b0, [x0, x1]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 %offset
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@@ -246,9 +282,11 @@ entry:
define double @fct14(i16* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct14:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr h0, [x0, x1, lsl #1]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 %offset
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@@ -259,9 +297,11 @@ entry:
define double @fct15(i32* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct15:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0, x1, lsl #2]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 %offset
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@@ -272,9 +312,11 @@ entry:
define double @fct16(i64* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct16:
-; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, x1, lsl #3]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr d0, [x0, x1, lsl #3]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 %offset
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@@ -285,11 +327,13 @@ entry:
; ********* 5. load with unscaled imm to float. *********
define float @fct17(i8* nocapture %sp0) {
-entry:
; CHECK-LABEL: fct17:
-; CHECK: ldur b[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldur b0, [x0, #-1]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
+entry:
%bitcast = ptrtoint i8* %sp0 to i64
%add = add i64 %bitcast, -1
%addr = inttoptr i64 %add to i8*
@@ -301,9 +345,11 @@ entry:
define float @fct18(i16* nocapture %sp0) {
; CHECK-LABEL: fct18:
-; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur h0, [x0, #1]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i16* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i16*
@@ -315,9 +361,11 @@ define float @fct18(i16* nocapture %sp0) {
define float @fct19(i32* nocapture %sp0) {
; CHECK-LABEL: fct19:
-; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur s0, [x0, #1]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i32* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i32*
@@ -330,9 +378,11 @@ define float @fct19(i32* nocapture %sp0) {
; i64 -> f32 is not supported on floating point unit.
define float @fct20(i64* nocapture %sp0) {
; CHECK-LABEL: fct20:
-; CHECK: ldur x[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur x8, [x0, #1]
+; CHECK-NEXT: ucvtf s0, x8
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i64* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i64*
@@ -345,11 +395,13 @@ define float @fct20(i64* nocapture %sp0) {
; ********* 6. load with unscaled imm to double. *********
define double @fct21(i8* nocapture %sp0) {
-entry:
; CHECK-LABEL: fct21:
-; CHECK: ldur b[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldur b0, [x0, #-1]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
+entry:
%bitcast = ptrtoint i8* %sp0 to i64
%add = add i64 %bitcast, -1
%addr = inttoptr i64 %add to i8*
@@ -361,9 +413,11 @@ entry:
define double @fct22(i16* nocapture %sp0) {
; CHECK-LABEL: fct22:
-; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur h0, [x0, #1]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i16* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i16*
@@ -375,9 +429,11 @@ define double @fct22(i16* nocapture %sp0) {
define double @fct23(i32* nocapture %sp0) {
; CHECK-LABEL: fct23:
-; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur s0, [x0, #1]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i32* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i32*
@@ -389,9 +445,11 @@ define double @fct23(i32* nocapture %sp0) {
define double @fct24(i64* nocapture %sp0) {
; CHECK-LABEL: fct24:
-; CHECK: ldur d[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur d0, [x0, #1]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i64* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i64*
@@ -404,16 +462,21 @@ define double @fct24(i64* nocapture %sp0) {
; ********* 1s. load with scaled imm to float. *********
define float @sfct1(i8* nocapture %sp0) {
-; CHECK-LABEL: sfct1:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK-CYC-LABEL: sfct1:
+; CHECK-CYC: // %bb.0: // %entry
+; CHECK-CYC-NEXT: ldr b0, [x0, #1]
+; CHECK-CYC-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-CYC-NEXT: scvtf s0, s0
+; CHECK-CYC-NEXT: fmul s0, s0, s0
+; CHECK-CYC-NEXT: ret
+;
; CHECK-A57-LABEL: sfct1:
-; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
-; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK-A57: // %bb.0: // %entry
+; CHECK-A57-NEXT: ldrsb w8, [x0, #1]
+; CHECK-A57-NEXT: scvtf s0, w8
+; CHECK-A57-NEXT: fmul s0, s0, s0
+; CHECK-A57-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 1
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@@ -424,10 +487,12 @@ entry:
define float @sfct2(i16* nocapture %sp0) {
; CHECK-LABEL: sfct2:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr h0, [x0, #2]
+; CHECK-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 1
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@@ -438,9 +503,11 @@ entry:
define float @sfct3(i32* nocapture %sp0) {
; CHECK-LABEL: sfct3:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0, #4]
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 1
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@@ -452,9 +519,11 @@ entry:
; i64 -> f32 is not supported on floating point unit.
define float @sfct4(i64* nocapture %sp0) {
; CHECK-LABEL: sfct4:
-; CHECK: ldr x[[REGNUM:[0-9]+]], [x0, #8]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr x8, [x0, #8]
+; CHECK-NEXT: scvtf s0, x8
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 1
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@@ -465,16 +534,21 @@ entry:
; ********* 2s. load with scaled register to float. *********
define float @sfct5(i8* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: sfct5:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK-CYC-LABEL: sfct5:
+; CHECK-CYC: // %bb.0: // %entry
+; CHECK-CYC-NEXT: ldr b0, [x0, x1]
+; CHECK-CYC-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-CYC-NEXT: scvtf s0, s0
+; CHECK-CYC-NEXT: fmul s0, s0, s0
+; CHECK-CYC-NEXT: ret
+;
; CHECK-A57-LABEL: sfct5:
-; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
-; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK-A57: // %bb.0: // %entry
+; CHECK-A57-NEXT: ldrsb w8, [x0, x1]
+; CHECK-A57-NEXT: scvtf s0, w8
+; CHECK-A57-NEXT: fmul s0, s0, s0
+; CHECK-A57-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 %offset
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@@ -485,10 +559,12 @@ entry:
define float @sfct6(i16* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: sfct6:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr h0, [x0, x1, lsl #1]
+; CHECK-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 %offset
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@@ -499,9 +575,11 @@ entry:
define float @sfct7(i32* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: sfct7:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0, x1, lsl #2]
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 %offset
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@@ -513,9 +591,11 @@ entry:
; i64 -> f32 is not supported on floating point unit.
define float @sfct8(i64* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: sfct8:
-; CHECK: ldr x[[REGNUM:[0-9]+]], [x0, x1, lsl #3]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr x8, [x0, x1, lsl #3]
+; CHECK-NEXT: scvtf s0, x8
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 %offset
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@@ -527,9 +607,11 @@ entry:
; ********* 3s. load with scaled imm to double. *********
define double @sfct9(i8* nocapture %sp0) {
; CHECK-LABEL: sfct9:
-; CHECK: ldrsb w[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldrsb w8, [x0, #1]
+; CHECK-NEXT: scvtf d0, w8
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 1
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@@ -539,16 +621,21 @@ entry:
}
define double @sfct10(i16* nocapture %sp0) {
-; CHECK-LABEL: sfct10:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK-CYC-LABEL: sfct10:
+; CHECK-CYC: // %bb.0: // %entry
+; CHECK-CYC-NEXT: ldr h0, [x0, #2]
+; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-CYC-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-CYC-NEXT: scvtf d0, d0
+; CHECK-CYC-NEXT: fmul d0, d0, d0
+; CHECK-CYC-NEXT: ret
+;
; CHECK-A57-LABEL: sfct10:
-; CHECK-A57: ldrsh w[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK-A57: // %bb.0: // %entry
+; CHECK-A57-NEXT: ldrsh w8, [x0, #2]
+; CHECK-A57-NEXT: scvtf d0, w8
+; CHECK-A57-NEXT: fmul d0, d0, d0
+; CHECK-A57-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 1
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@@ -559,10 +646,12 @@ entry:
define double @sfct11(i32* nocapture %sp0) {
; CHECK-LABEL: sfct11:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0, #4]
+; CHECK-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-NEXT: scvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 1
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@@ -573,9 +662,11 @@ entry:
define double @sfct12(i64* nocapture %sp0) {
; CHECK-LABEL: sfct12:
-; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, #8]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr d0, [x0, #8]
+; CHECK-NEXT: scvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 1
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@@ -587,9 +678,11 @@ entry:
; ********* 4s. load with scaled register to double. *********
define double @sfct13(i8* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: sfct13:
-; CHECK: ldrsb w[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldrsb w8, [x0, x1]
+; CHECK-NEXT: scvtf d0, w8
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 %offset
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@@ -599,16 +692,21 @@ entry:
}
define double @sfct14(i16* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: sfct14:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK-CYC-LABEL: sfct14:
+; CHECK-CYC: // %bb.0: // %entry
+; CHECK-CYC-NEXT: ldr h0, [x0, x1, lsl #1]
+; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-CYC-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-CYC-NEXT: scvtf d0, d0
+; CHECK-CYC-NEXT: fmul d0, d0, d0
+; CHECK-CYC-NEXT: ret
+;
; CHECK-A57-LABEL: sfct14:
-; CHECK-A57: ldrsh w[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK-A57: // %bb.0: // %entry
+; CHECK-A57-NEXT: ldrsh w8, [x0, x1, lsl #1]
+; CHECK-A57-NEXT: scvtf d0, w8
+; CHECK-A57-NEXT: fmul d0, d0, d0
+; CHECK-A57-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 %offset
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@@ -619,10 +717,12 @@ entry:
define double @sfct15(i32* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: sfct15:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0, x1, lsl #2]
+; CHECK-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-NEXT: scvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 %offset
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@@ -633,9 +733,11 @@ entry:
define double @sfct16(i64* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: sfct16:
-; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, x1, lsl #3]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr d0, [x0, x1, lsl #3]
+; CHECK-NEXT: scvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 %offset
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@@ -646,17 +748,22 @@ entry:
; ********* 5s. load with unscaled imm to float. *********
define float @sfct17(i8* nocapture %sp0) {
-entry:
-; CHECK-LABEL: sfct17:
-; CHECK: ldur b[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK-CYC-LABEL: sfct17:
+; CHECK-CYC: // %bb.0: // %entry
+; CHECK-CYC-NEXT: ldur b0, [x0, #-1]
+; CHECK-CYC-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-CYC-NEXT: scvtf s0, s0
+; CHECK-CYC-NEXT: fmul s0, s0, s0
+; CHECK-CYC-NEXT: ret
+;
; CHECK-A57-LABEL: sfct17:
-; CHECK-A57: ldursb w[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
-; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK-A57: // %bb.0: // %entry
+; CHECK-A57-NEXT: ldursb w8, [x0, #-1]
+; CHECK-A57-NEXT: scvtf s0, w8
+; CHECK-A57-NEXT: fmul s0, s0, s0
+; CHECK-A57-NEXT: ret
+entry:
%bitcast = ptrtoint i8* %sp0 to i64
%add = add i64 %bitcast, -1
%addr = inttoptr i64 %add to i8*
@@ -668,10 +775,12 @@ entry:
define float @sfct18(i16* nocapture %sp0) {
; CHECK-LABEL: sfct18:
-; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur h0, [x0, #1]
+; CHECK-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i16* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i16*
@@ -683,9 +792,11 @@ define float @sfct18(i16* nocapture %sp0) {
define float @sfct19(i32* nocapture %sp0) {
; CHECK-LABEL: sfct19:
-; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur s0, [x0, #1]
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i32* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i32*
@@ -698,9 +809,11 @@ define float @sfct19(i32* nocapture %sp0) {
; i64 -> f32 is not supported on floating point unit.
define float @sfct20(i64* nocapture %sp0) {
; CHECK-LABEL: sfct20:
-; CHECK: ldur x[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur x8, [x0, #1]
+; CHECK-NEXT: scvtf s0, x8
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i64* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i64*
@@ -713,11 +826,13 @@ define float @sfct20(i64* nocapture %sp0) {
; ********* 6s. load with unscaled imm to double. *********
define double @sfct21(i8* nocapture %sp0) {
-entry:
; CHECK-LABEL: sfct21:
-; CHECK: ldursb w[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldursb w8, [x0, #-1]
+; CHECK-NEXT: scvtf d0, w8
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
+entry:
%bitcast = ptrtoint i8* %sp0 to i64
%add = add i64 %bitcast, -1
%addr = inttoptr i64 %add to i8*
@@ -728,16 +843,21 @@ entry:
}
define double @sfct22(i16* nocapture %sp0) {
-; CHECK-LABEL: sfct22:
-; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK-CYC-LABEL: sfct22:
+; CHECK-CYC: // %bb.0:
+; CHECK-CYC-NEXT: ldur h0, [x0, #1]
+; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-CYC-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-CYC-NEXT: scvtf d0, d0
+; CHECK-CYC-NEXT: fmul d0, d0, d0
+; CHECK-CYC-NEXT: ret
+;
; CHECK-A57-LABEL: sfct22:
-; CHECK-A57: ldursh w[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK-A57: // %bb.0:
+; CHECK-A57-NEXT: ldursh w8, [x0, #1]
+; CHECK-A57-NEXT: scvtf d0, w8
+; CHECK-A57-NEXT: fmul d0, d0, d0
+; CHECK-A57-NEXT: ret
%bitcast = ptrtoint i16* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i16*
@@ -749,10 +869,12 @@ define double @sfct22(i16* nocapture %sp0) {
define double @sfct23(i32* nocapture %sp0) {
; CHECK-LABEL: sfct23:
-; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur s0, [x0, #1]
+; CHECK-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-NEXT: scvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i32* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i32*
@@ -764,9 +886,11 @@ define double @sfct23(i32* nocapture %sp0) {
define double @sfct24(i64* nocapture %sp0) {
; CHECK-LABEL: sfct24:
-; CHECK: ldur d[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldur d0, [x0, #1]
+; CHECK-NEXT: scvtf d0, d0
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
%bitcast = ptrtoint i64* %sp0 to i64
%add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i64*
@@ -779,11 +903,13 @@ define double @sfct24(i64* nocapture %sp0) {
; Check that we do not use SSHLL code sequence when code size is a concern.
define float @codesize_sfct17(i8* nocapture %sp0) optsize {
-entry:
; CHECK-LABEL: codesize_sfct17:
-; CHECK: ldursb w[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldursb w8, [x0, #-1]
+; CHECK-NEXT: scvtf s0, w8
+; CHECK-NEXT: fmul s0, s0, s0
+; CHECK-NEXT: ret
+entry:
%bitcast = ptrtoint i8* %sp0 to i64
%add = add i64 %bitcast, -1
%addr = inttoptr i64 %add to i8*
@@ -794,10 +920,12 @@ entry:
}
define double @codesize_sfct11(i32* nocapture %sp0) minsize {
-; CHECK-LABEL: sfct11:
-; CHECK: ldr w[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
+; CHECK-LABEL: codesize_sfct11:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr w8, [x0, #4]
+; CHECK-NEXT: scvtf d0, w8
+; CHECK-NEXT: fmul d0, d0, d0
+; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 1
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@@ -813,42 +941,78 @@ entry:
define float @float_from_i128(i128 %in) {
; CHECK-LABEL: float_from_i128:
-; CHECK: bl {{_?__floatuntisf}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl __floatuntisf
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%conv = uitofp i128 %in to float
ret float %conv
}
define double @double_from_i128(i128 %in) {
; CHECK-LABEL: double_from_i128:
-; CHECK: bl {{_?__floattidf}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl __floattidf
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%conv = sitofp i128 %in to double
ret double %conv
}
define fp128 @fp128_from_i128(i128 %in) {
; CHECK-LABEL: fp128_from_i128:
-; CHECK: bl {{_?__floatuntitf}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl __floatuntitf
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%conv = uitofp i128 %in to fp128
ret fp128 %conv
}
define i128 @i128_from_float(float %in) {
-; CHECK-LABEL: i128_from_float
-; CHECK: bl {{_?__fixsfti}}
+; CHECK-LABEL: i128_from_float:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%conv = fptosi float %in to i128
ret i128 %conv
}
define i128 @i128_from_double(double %in) {
-; CHECK-LABEL: i128_from_double
-; CHECK: bl {{_?__fixunsdfti}}
+; CHECK-LABEL: i128_from_double:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl __fixunsdfti
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%conv = fptoui double %in to i128
ret i128 %conv
}
define i128 @i128_from_fp128(fp128 %in) {
-; CHECK-LABEL: i128_from_fp128
-; CHECK: bl {{_?__fixtfti}}
+; CHECK-LABEL: i128_from_fp128:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl __fixtfti
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%conv = fptosi fp128 %in to i128
ret i128 %conv
}
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