[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

Mon May 16 00:24:40 PDT 2022

dmgreen added a comment.

In D123782#3514938 <https://reviews.llvm.org/D123782#3514938>, @rahular-rrlogic wrote:

> In D123782#3508832 <https://reviews.llvm.org/D123782#3508832>, @dmgreen wrote:
>
>> Thanks for the update. Have you tried a bootstrap to make sure it passes now?
>
> I never had any test failures even in the previous revision. How do I include all tests?

Do you mean just ninja check-all? Those tests will only include the tests people have deemed worth adding in the past - they cannot cover all the possible cases and combinations of things that can come up. To run more thorough testing you need to start compiling code with the new compiler and making sure the results are correct.  The issue that came up I think was when the compiler compiled itself - a bootstrap. We should make sure that doesn't still happen in the same way.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782