[llvm] 49b0c60 - [DivRemPairs][Mips] Pre-commit test for Mips target
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Sun May 15 23:42:41 PDT 2022
Author: Jim Lin
Date: 2022-05-16T14:45:40+08:00
New Revision: 49b0c605424b7e54cd7c287563f3650bcd7f0382
URL: https://github.com/llvm/llvm-project/commit/49b0c605424b7e54cd7c287563f3650bcd7f0382
DIFF: https://github.com/llvm/llvm-project/commit/49b0c605424b7e54cd7c287563f3650bcd7f0382.diff
LOG: [DivRemPairs][Mips] Pre-commit test for Mips target
Copied from PowerPC.
Reviewed By: sdardis
Differential Revision: https://reviews.llvm.org/D124979
Added:
llvm/test/Transforms/DivRemPairs/Mips/div-expanded-rem-pair.ll
llvm/test/Transforms/DivRemPairs/Mips/div-rem-pairs.ll
llvm/test/Transforms/DivRemPairs/Mips/lit.local.cfg
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/DivRemPairs/Mips/div-expanded-rem-pair.ll b/llvm/test/Transforms/DivRemPairs/Mips/div-expanded-rem-pair.ll
new file mode 100644
index 0000000000000..45946c4505e4d
--- /dev/null
+++ b/llvm/test/Transforms/DivRemPairs/Mips/div-expanded-rem-pair.ll
@@ -0,0 +1,175 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -div-rem-pairs -S -mtriple=mips-unknown-unknown | FileCheck %s
+
+declare void @foo(i32, i32)
+
+define void @decompose_illegal_srem_same_block(i32 %a, i32 %b) {
+; CHECK-LABEL: @decompose_illegal_srem_same_block(
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[T0:%.*]] = mul i32 [[DIV]], [[B]]
+; CHECK-NEXT: [[REM:%.*]] = sub i32 [[A]], [[T0]]
+; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
+; CHECK-NEXT: ret void
+;
+ %div = sdiv i32 %a, %b
+ %t0 = mul i32 %div, %b
+ %rem = sub i32 %a, %t0
+ call void @foo(i32 %rem, i32 %div)
+ ret void
+}
+
+define void @decompose_illegal_urem_same_block(i32 %a, i32 %b) {
+; CHECK-LABEL: @decompose_illegal_urem_same_block(
+; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[T0:%.*]] = mul i32 [[DIV]], [[B]]
+; CHECK-NEXT: [[REM:%.*]] = sub i32 [[A]], [[T0]]
+; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
+; CHECK-NEXT: ret void
+;
+ %div = udiv i32 %a, %b
+ %t0 = mul i32 %div, %b
+ %rem = sub i32 %a, %t0
+ call void @foo(i32 %rem, i32 %div)
+ ret void
+}
+
+; Recompose and hoist the srem if it's safe and free, otherwise keep as-is..
+
+define i16 @hoist_srem(i16 %a, i16 %b) {
+; CHECK-LABEL: @hoist_srem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i16 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[DIV]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[T0:%.*]] = mul i16 [[DIV]], [[B]]
+; CHECK-NEXT: [[REM:%.*]] = sub i16 [[A]], [[T0]]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i16 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i16 [[RET]]
+;
+entry:
+ %div = sdiv i16 %a, %b
+ %cmp = icmp eq i16 %div, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %t0 = mul i16 %div, %b
+ %rem = sub i16 %a, %t0
+ br label %end
+
+end:
+ %ret = phi i16 [ %rem, %if ], [ 3, %entry ]
+ ret i16 %ret
+}
+
+; Recompose and hoist the urem if it's safe and free, otherwise keep as-is..
+
+define i8 @hoist_urem(i8 %a, i8 %b) {
+; CHECK-LABEL: @hoist_urem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[DIV:%.*]] = udiv i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[DIV]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[T0:%.*]] = mul i8 [[DIV]], [[B]]
+; CHECK-NEXT: [[REM:%.*]] = sub i8 [[A]], [[T0]]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i8 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i8 [[RET]]
+;
+entry:
+ %div = udiv i8 %a, %b
+ %cmp = icmp eq i8 %div, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %t0 = mul i8 %div, %b
+ %rem = sub i8 %a, %t0
+ br label %end
+
+end:
+ %ret = phi i8 [ %rem, %if ], [ 3, %entry ]
+ ret i8 %ret
+}
+
+; Be careful with RAUW/invalidation if this is a srem-of-srem.
+
+define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
+; CHECK-LABEL: @srem_of_srem_unexpanded(
+; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[X_FROZEN:%.*]] = freeze i32 [[X:%.*]]
+; CHECK-NEXT: [[T0_FROZEN:%.*]] = freeze i32 [[T0]]
+; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X_FROZEN]], [[T0_FROZEN]]
+; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[T1]], [[T0_FROZEN]]
+; CHECK-NEXT: [[T3_DECOMPOSED:%.*]] = sub i32 [[X_FROZEN]], [[TMP1]]
+; CHECK-NEXT: [[Y_FROZEN:%.*]] = freeze i32 [[Y]]
+; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_DECOMPOSED]], [[Y_FROZEN]]
+; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
+; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[T4]], [[Y_FROZEN]]
+; CHECK-NEXT: [[T6_DECOMPOSED:%.*]] = sub i32 [[T3_DECOMPOSED]], [[TMP2]]
+; CHECK-NEXT: ret i32 [[T6_DECOMPOSED]]
+;
+ %t0 = mul nsw i32 %Z, %Y
+ %t1 = sdiv i32 %X, %t0
+ %t2 = mul nsw i32 %t0, %t1
+ %t3 = srem i32 %X, %t0
+ %t4 = sdiv i32 %t3, %Y
+ %t5 = mul nsw i32 %t4, %Y
+ %t6 = srem i32 %t3, %Y
+ ret i32 %t6
+}
+define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
+; CHECK-LABEL: @srem_of_srem_expanded(
+; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
+; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
+; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
+; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
+; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
+; CHECK-NEXT: ret i32 [[T6]]
+;
+ %t0 = mul nsw i32 %Z, %Y
+ %t1 = sdiv i32 %X, %t0
+ %t2 = mul nsw i32 %t0, %t1
+ %t3 = sub nsw i32 %X, %t2
+ %t4 = sdiv i32 %t3, %Y
+ %t5 = mul nsw i32 %t4, %Y
+ %t6 = sub nsw i32 %t3, %t5
+ ret i32 %t6
+}
+
+; If the target doesn't have a unified div/rem op for the type, keep decomposed rem
+
+define i128 @dont_hoist_urem(i128 %a, i128 %b) {
+; CHECK-LABEL: @dont_hoist_urem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[DIV:%.*]] = udiv i128 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[DIV]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[T0:%.*]] = mul i128 [[DIV]], [[B]]
+; CHECK-NEXT: [[REM:%.*]] = sub i128 [[A]], [[T0]]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i128 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i128 [[RET]]
+;
+entry:
+ %div = udiv i128 %a, %b
+ %cmp = icmp eq i128 %div, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %t0 = mul i128 %div, %b
+ %rem = sub i128 %a, %t0
+ br label %end
+
+end:
+ %ret = phi i128 [ %rem, %if ], [ 3, %entry ]
+ ret i128 %ret
+}
diff --git a/llvm/test/Transforms/DivRemPairs/Mips/div-rem-pairs.ll b/llvm/test/Transforms/DivRemPairs/Mips/div-rem-pairs.ll
new file mode 100644
index 0000000000000..96433204c7f79
--- /dev/null
+++ b/llvm/test/Transforms/DivRemPairs/Mips/div-rem-pairs.ll
@@ -0,0 +1,366 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -div-rem-pairs -S -mtriple=mips-unknown-unknown | FileCheck %s
+
+declare void @foo(i32, i32)
+
+define void @decompose_illegal_srem_same_block(i32 %a, i32 %b) {
+; CHECK-LABEL: @decompose_illegal_srem_same_block(
+; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i32 [[A:%.*]]
+; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i32 [[B:%.*]]
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A_FROZEN]], [[B_FROZEN]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[B_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[A_FROZEN]], [[TMP1]]
+; CHECK-NEXT: call void @foo(i32 [[REM_DECOMPOSED]], i32 [[DIV]])
+; CHECK-NEXT: ret void
+;
+ %rem = srem i32 %a, %b
+ %div = sdiv i32 %a, %b
+ call void @foo(i32 %rem, i32 %div)
+ ret void
+}
+
+define void @decompose_illegal_urem_same_block(i32 %a, i32 %b) {
+; CHECK-LABEL: @decompose_illegal_urem_same_block(
+; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i32 [[A:%.*]]
+; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i32 [[B:%.*]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A_FROZEN]], [[B_FROZEN]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[B_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[A_FROZEN]], [[TMP1]]
+; CHECK-NEXT: call void @foo(i32 [[REM_DECOMPOSED]], i32 [[DIV]])
+; CHECK-NEXT: ret void
+;
+ %div = udiv i32 %a, %b
+ %rem = urem i32 %a, %b
+ call void @foo(i32 %rem, i32 %div)
+ ret void
+}
+
+; Hoist and optionally decompose the sdiv because it's safe and free.
+; PR31028 - https://bugs.llvm.org/show_bug.cgi?id=31028
+
+define i32 @hoist_sdiv(i32 %a, i32 %b) {
+; CHECK-LABEL: @hoist_sdiv(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i32 [[A:%.*]]
+; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i32 [[B:%.*]]
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A_FROZEN]], [[B_FROZEN]]
+; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[DIV]], [[B_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[A_FROZEN]], [[TMP0]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM_DECOMPOSED]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[DIV]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+entry:
+ %rem = srem i32 %a, %b
+ %cmp = icmp eq i32 %rem, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %div = sdiv i32 %a, %b
+ br label %end
+
+end:
+ %ret = phi i32 [ %div, %if ], [ 3, %entry ]
+ ret i32 %ret
+}
+
+; Hoist and optionally decompose the udiv because it's safe and free.
+
+define i64 @hoist_udiv(i64 %a, i64 %b) {
+; CHECK-LABEL: @hoist_udiv(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i64 [[A:%.*]]
+; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[A_FROZEN]], [[B_FROZEN]]
+; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[DIV]], [[B_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i64 [[A_FROZEN]], [[TMP0]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[REM_DECOMPOSED]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i64 [ [[DIV]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i64 [[RET]]
+;
+entry:
+ %rem = urem i64 %a, %b
+ %cmp = icmp eq i64 %rem, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %div = udiv i64 %a, %b
+ br label %end
+
+end:
+ %ret = phi i64 [ %div, %if ], [ 3, %entry ]
+ ret i64 %ret
+}
+
+; Hoist the srem if it's safe and free, otherwise decompose it.
+
+define i16 @hoist_srem(i16 %a, i16 %b) {
+; CHECK-LABEL: @hoist_srem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i16 [[A:%.*]]
+; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i16 [[B:%.*]]
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i16 [[A_FROZEN]], [[B_FROZEN]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[DIV]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[TMP0:%.*]] = mul i16 [[DIV]], [[B_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i16 [[A_FROZEN]], [[TMP0]]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i16 [ [[REM_DECOMPOSED]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i16 [[RET]]
+;
+entry:
+ %div = sdiv i16 %a, %b
+ %cmp = icmp eq i16 %div, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %rem = srem i16 %a, %b
+ br label %end
+
+end:
+ %ret = phi i16 [ %rem, %if ], [ 3, %entry ]
+ ret i16 %ret
+}
+
+; Hoist the urem if it's safe and free, otherwise decompose it.
+
+define i8 @hoist_urem(i8 %a, i8 %b) {
+; CHECK-LABEL: @hoist_urem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i8 [[A:%.*]]
+; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i8 [[B:%.*]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv i8 [[A_FROZEN]], [[B_FROZEN]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[DIV]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[TMP0:%.*]] = mul i8 [[DIV]], [[B_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i8 [[A_FROZEN]], [[TMP0]]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i8 [ [[REM_DECOMPOSED]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i8 [[RET]]
+;
+entry:
+ %div = udiv i8 %a, %b
+ %cmp = icmp eq i8 %div, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %rem = urem i8 %a, %b
+ br label %end
+
+end:
+ %ret = phi i8 [ %rem, %if ], [ 3, %entry ]
+ ret i8 %ret
+}
+
+; Be careful with RAUW/invalidation if this is a srem-of-srem.
+
+define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
+; CHECK-LABEL: @srem_of_srem_unexpanded(
+; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[X_FROZEN:%.*]] = freeze i32 [[X:%.*]]
+; CHECK-NEXT: [[T0_FROZEN:%.*]] = freeze i32 [[T0]]
+; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X_FROZEN]], [[T0_FROZEN]]
+; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[T1]], [[T0_FROZEN]]
+; CHECK-NEXT: [[T3_DECOMPOSED:%.*]] = sub i32 [[X_FROZEN]], [[TMP1]]
+; CHECK-NEXT: [[Y_FROZEN:%.*]] = freeze i32 [[Y]]
+; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_DECOMPOSED]], [[Y_FROZEN]]
+; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
+; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[T4]], [[Y_FROZEN]]
+; CHECK-NEXT: [[T6_DECOMPOSED:%.*]] = sub i32 [[T3_DECOMPOSED]], [[TMP2]]
+; CHECK-NEXT: ret i32 [[T6_DECOMPOSED]]
+;
+ %t0 = mul nsw i32 %Z, %Y
+ %t1 = sdiv i32 %X, %t0
+ %t2 = mul nsw i32 %t0, %t1
+ %t3 = srem i32 %X, %t0
+ %t4 = sdiv i32 %t3, %Y
+ %t5 = mul nsw i32 %t4, %Y
+ %t6 = srem i32 %t3, %Y
+ ret i32 %t6
+}
+define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
+; CHECK-LABEL: @srem_of_srem_expanded(
+; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
+; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
+; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
+; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
+; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
+; CHECK-NEXT: ret i32 [[T6]]
+;
+ %t0 = mul nsw i32 %Z, %Y
+ %t1 = sdiv i32 %X, %t0
+ %t2 = mul nsw i32 %t0, %t1
+ %t3 = sub nsw i32 %X, %t2
+ %t4 = sdiv i32 %t3, %Y
+ %t5 = mul nsw i32 %t4, %Y
+ %t6 = sub nsw i32 %t3, %t5
+ ret i32 %t6
+}
+
+; If the ops don't match, don't do anything: signedness.
+
+define i32 @dont_hoist_udiv(i32 %a, i32 %b) {
+; CHECK-LABEL: @dont_hoist_udiv(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A]], [[B]]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[DIV]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+entry:
+ %rem = srem i32 %a, %b
+ %cmp = icmp eq i32 %rem, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %div = udiv i32 %a, %b
+ br label %end
+
+end:
+ %ret = phi i32 [ %div, %if ], [ 3, %entry ]
+ ret i32 %ret
+}
+
+; If the ops don't match, don't do anything: operation.
+
+define i32 @dont_hoist_srem(i32 %a, i32 %b) {
+; CHECK-LABEL: @dont_hoist_srem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[REM:%.*]] = urem i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[REM2:%.*]] = srem i32 [[A]], [[B]]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[REM2]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+entry:
+ %rem = urem i32 %a, %b
+ %cmp = icmp eq i32 %rem, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %rem2 = srem i32 %a, %b
+ br label %end
+
+end:
+ %ret = phi i32 [ %rem2, %if ], [ 3, %entry ]
+ ret i32 %ret
+}
+
+; If the ops don't match, don't do anything: operands.
+
+define i32 @dont_hoist_sdiv(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @dont_hoist_sdiv(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A]], [[C:%.*]]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[DIV]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+entry:
+ %rem = srem i32 %a, %b
+ %cmp = icmp eq i32 %rem, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %div = sdiv i32 %a, %c
+ br label %end
+
+end:
+ %ret = phi i32 [ %div, %if ], [ 3, %entry ]
+ ret i32 %ret
+}
+
+; If the target doesn't have a unified div/rem op for the type, decompose rem in-place to mul+sub.
+
+define i128 @dont_hoist_urem(i128 %a, i128 %b) {
+; CHECK-LABEL: @dont_hoist_urem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i128 [[A:%.*]]
+; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i128 [[B:%.*]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv i128 [[A_FROZEN]], [[B_FROZEN]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[DIV]], 42
+; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[TMP0:%.*]] = mul i128 [[DIV]], [[B_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i128 [[A_FROZEN]], [[TMP0]]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i128 [ [[REM_DECOMPOSED]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i128 [[RET]]
+;
+entry:
+ %div = udiv i128 %a, %b
+ %cmp = icmp eq i128 %div, 42
+ br i1 %cmp, label %if, label %end
+
+if:
+ %rem = urem i128 %a, %b
+ br label %end
+
+end:
+ %ret = phi i128 [ %rem, %if ], [ 3, %entry ]
+ ret i128 %ret
+}
+
+; We don't hoist if one op does not dominate the other,
+; but we could hoist both ops to the common predecessor block?
+
+define i32 @no_domination(i1 %cmp, i32 %a, i32 %b) {
+; CHECK-LABEL: @no_domination(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[CMP:%.*]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: br label [[END:%.*]]
+; CHECK: else:
+; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A]], [[B]]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[DIV]], [[IF]] ], [ [[REM]], [[ELSE]] ]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+entry:
+ br i1 %cmp, label %if, label %else
+
+if:
+ %div = sdiv i32 %a, %b
+ br label %end
+
+else:
+ %rem = srem i32 %a, %b
+ br label %end
+
+end:
+ %ret = phi i32 [ %div, %if ], [ %rem, %else ]
+ ret i32 %ret
+}
+
diff --git a/llvm/test/Transforms/DivRemPairs/Mips/lit.local.cfg b/llvm/test/Transforms/DivRemPairs/Mips/lit.local.cfg
new file mode 100644
index 0000000000000..7d12f7a9c5649
--- /dev/null
+++ b/llvm/test/Transforms/DivRemPairs/Mips/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'Mips' in config.root.targets:
+ config.unsupported = True
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