[PATCH] D125657: [RegisterCoalescer] fix dst subreg replacement during remat copy trick

[Afanasyev Ivan via Phabricator via llvm-commits]

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Instructions might use definition register as its "undef" operand. It happens on architectures with predicated execiton:

  %0:subreg = instruction op_1, ..., op_N, undef %0:subreg, op_N+2, ...

RegisterCoalescer should take into account all remat instruction operands during destination subregister fixup.

  ; remat result before fix:
  %1 = instruction op_1, ..., op_N, undef %1:subreg, op_N+2, ...
  
  ; remat result after fix (correct):
  %1 = instruction op_1, ..., op_N, undef %1, op_N+2, ...


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125657

Files:
  llvm/lib/CodeGen/RegisterCoalescer.cpp


Index: llvm/lib/CodeGen/RegisterCoalescer.cpp
===================================================================
--- llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1379,8 +1379,19 @@
         TRI->getCommonSubClass(DefRC, DstRC);
       if (CommonRC != nullptr) {
         NewRC = CommonRC;
+
+        // Instruction might contain "undef %0:subreg" as use operand:
+        //   %0:subreg = insrt op_1, ..., op_N, undef %0:subreg, op_N+2, ...
+        //
+        // Need to check all operands.
+        for (MachineOperand &MO : NewMI.operands()) {
+          if (MO.isReg() && MO.getReg() == DstReg &&
+              MO.getSubReg() == DstIdx) {
+              MO.setSubReg(0);
+          }
+        }
+
         DstIdx = 0;
-        DefMO.setSubReg(0);
         DefMO.setIsUndef(false); // Only subregs can have def+undef.
       }
     }


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