[PATCH] D125641: [DAGCombiner] Fix bug in MatchBSwapHWordLow.

[Craig Topper via Phabricator via llvm-commits]

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This function tries to match (a >> 8) | (a << 8) as (bswap a) >> 16.

If the SRL isn't masked and the high bits aren't demanded, we still
need to ensure that bits 23:16 are zero. After the right shift they
will be in bits 15:8 which is where the important bits from the SHL
end up. It's only a bswap if the OR on bits 15:8 only takes the bits
from the SHL.

Fixes PR55484.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125641

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/arm64-rev.ll
  llvm/test/CodeGen/ARM/rev.ll
  llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
  llvm/test/CodeGen/Thumb/rev.ll
  llvm/test/CodeGen/X86/bswap.ll

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