[PATCH] D125512: [NVPTX] Enable AtomicExpandPass for NVPTX, and add the check for atomicrmw

[Shilei Tian via Phabricator via llvm-commits]

tianshilei1992 updated this revision to Diff 429551.
tianshilei1992 added a comment.

add test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125512/new/

https://reviews.llvm.org/D125512

Files:
  llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
  llvm/lib/Target/NVPTX/NVPTXISelLowering.h
  llvm/test/CodeGen/NVPTX/atomic-expand.ll


Index: llvm/test/CodeGen/NVPTX/atomic-expand.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/NVPTX/atomic-expand.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=CHECK-SM20
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 | FileCheck %s --check-prefix=CHECK-SM60
+; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
+; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_60 | %ptxas-verify %}
+
+; CHECK-LABEL: foo
+define void @foo(ptr %0, double %1) {
+entry:
+  ; CHECK-SM20: atom.cas.b64
+  ; CHECK-SM60: atom.add.f64
+  %2 = atomicrmw fadd ptr %0, double %1 monotonic, align 8
+  ret void
+}
Index: llvm/lib/Target/NVPTX/NVPTXISelLowering.h
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+++ llvm/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -561,6 +561,9 @@
   // instruction, so we say that ctlz is cheap to speculate.
   bool isCheapToSpeculateCtlz() const override { return true; }
 
+  AtomicExpansionKind
+  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
+
 private:
   const NVPTXSubtarget &STI; // cache the subtarget here
   SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
Index: llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -5125,6 +5125,46 @@
   }
 }
 
+NVPTXTargetLowering::AtomicExpansionKind
+NVPTXTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
+  Type *Ty = AI->getValOperand()->getType();
+  if (AI->isFloatingPointOperation()) {
+    if (AI->getOperation() == AtomicRMWInst::BinOp::FAdd) {
+      if (Ty->isFloatTy())
+        return AtomicExpansionKind::None;
+      if (Ty->isDoubleTy() && STI.hasAtomAddF64())
+        return AtomicExpansionKind::None;
+    }
+    return AtomicExpansionKind::CmpXChg;
+  }
+
+  switch (AI->getOperation()) {
+  default:
+    return AtomicExpansionKind::CmpXChg;
+  case AtomicRMWInst::BinOp::Add:
+  case AtomicRMWInst::BinOp::Sub:
+  case AtomicRMWInst::BinOp::Max:
+  case AtomicRMWInst::BinOp::Min:
+  case AtomicRMWInst::BinOp::UMax:
+  case AtomicRMWInst::BinOp::UMin:
+  case AtomicRMWInst::BinOp::Xchg:
+  case AtomicRMWInst::BinOp::And:
+  case AtomicRMWInst::BinOp::Or:
+  case AtomicRMWInst::BinOp::Xor:
+    assert(Ty->isIntegerTy());
+    switch (cast<llvm::IntegerType>(Ty)->getBitWidth()) {
+    case 32:
+      return AtomicExpansionKind::None;
+    case 64:
+      return AtomicExpansionKind::None;
+    default:
+      return AtomicExpansionKind::CmpXChg;
+    }
+  }
+
+  return AtomicExpansionKind::CmpXChg;
+}
+
 // Pin NVPTXTargetObjectFile's vtables to this file.
 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() = default;
 


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