[llvm] f863913 - [AArch64] Baseline test for D125307
Alex Richardson via llvm-commits
llvm-commits at lists.llvm.org
Sat May 14 07:43:18 PDT 2022
Author: Alex Richardson
Date: 2022-05-14T14:15:36Z
New Revision: f8639133b58dd7335474dfa9dbb04b13098c5294
URL: https://github.com/llvm/llvm-project/commit/f8639133b58dd7335474dfa9dbb04b13098c5294
DIFF: https://github.com/llvm/llvm-project/commit/f8639133b58dd7335474dfa9dbb04b13098c5294.diff
LOG: [AArch64] Baseline test for D125307
Differential Revision: https://reviews.llvm.org/D125240
Added:
llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll b/llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll
new file mode 100644
index 0000000000000..18bcfce05e801
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll
@@ -0,0 +1,322 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;; These test functions previously triggered the following error when emitting machine code:
+;; LLVM ERROR: Attempting to emit UCVTFv1i64 instruction but the Feature_HasNEON predicate(s) are not met
+; RUN: llc -mtriple=aarch64 -mattr=+neon,+fullfp16 < %s | FileCheck %s --check-prefixes=CHECK,NEON-ENABLED
+; RUN: llc -mtriple=aarch64 -mattr=-neon,+fullfp16 < %s | FileCheck %s --check-prefixes=CHECK,NEON-DISABLED
+;; Emit an object file so that verifyPredicates is called (it is not used for ASM output).
+; RUNTODO: llc -mtriple=aarch64 -mattr=-neon,+fullfp16 -o /dev/null %s --asm-show-inst -filetype=obj
+
+define double @ui8_to_double(i8* %i, float* %f) {
+; CHECK-LABEL: ui8_to_double:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr b0, [x0]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: ret
+entry:
+ %ld = load i8, i8* %i, align 1
+ %conv = uitofp i8 %ld to double
+ ret double %conv
+}
+
+define float @ui8_to_float(i8* %i, float* %f) {
+; CHECK-LABEL: ui8_to_float:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr b0, [x0]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: ret
+entry:
+ %ld = load i8, i8* %i, align 1
+ %conv = uitofp i8 %ld to float
+ ret float %conv
+}
+
+define half @ui8_to_half(i8* %i, half* %f) {
+; CHECK-LABEL: ui8_to_half:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldrb w8, [x0]
+; CHECK-NEXT: ucvtf h0, w8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i8, i8* %i, align 1
+ %conv = uitofp i8 %ld to half
+ ret half %conv
+}
+
+define double @ui16_to_double(i16* %i, float* %f) {
+; CHECK-LABEL: ui16_to_double:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr h0, [x0]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: ret
+entry:
+ %ld = load i16, i16* %i, align 1
+ %conv = uitofp i16 %ld to double
+ ret double %conv
+}
+
+define float @ui16_to_float(i16* %i, float* %f) {
+; CHECK-LABEL: ui16_to_float:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr h0, [x0]
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: ret
+entry:
+ %ld = load i16, i16* %i, align 1
+ %conv = uitofp i16 %ld to float
+ ret float %conv
+}
+
+define half @ui16_to_half(i16* %i, half* %f) {
+; CHECK-LABEL: ui16_to_half:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldrh w8, [x0]
+; CHECK-NEXT: ucvtf h0, w8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i16, i16* %i, align 1
+ %conv = uitofp i16 %ld to half
+ ret half %conv
+}
+
+define double @ui32_to_double(i32* %i, float* %f) {
+; CHECK-LABEL: ui32_to_double:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: ret
+entry:
+ %ld = load i32, i32* %i, align 1
+ %conv = uitofp i32 %ld to double
+ ret double %conv
+}
+
+define float @ui32_to_float(i32* %i, float* %f) {
+; NEON-ENABLED-LABEL: ui32_to_float:
+; NEON-ENABLED: // %bb.0: // %entry
+; NEON-ENABLED-NEXT: ldr s0, [x0]
+; NEON-ENABLED-NEXT: ucvtf s0, s0
+; NEON-ENABLED-NEXT: ret
+;
+; NEON-DISABLED-LABEL: ui32_to_float:
+; NEON-DISABLED: // %bb.0: // %entry
+; NEON-DISABLED-NEXT: ldr w8, [x0]
+; NEON-DISABLED-NEXT: ucvtf s0, w8
+; NEON-DISABLED-NEXT: ret
+entry:
+ %ld = load i32, i32* %i, align 1
+ %conv = uitofp i32 %ld to float
+ ret float %conv
+}
+
+define half @ui32_to_half(i32* %i, half* %f) {
+; CHECK-LABEL: ui32_to_half:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: ucvtf h0, w8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i32, i32* %i, align 1
+ %conv = uitofp i32 %ld to half
+ ret half %conv
+}
+
+define double @ui64_to_double(i64* %i, float* %f) {
+; NEON-ENABLED-LABEL: ui64_to_double:
+; NEON-ENABLED: // %bb.0: // %entry
+; NEON-ENABLED-NEXT: ldr d0, [x0]
+; NEON-ENABLED-NEXT: ucvtf d0, d0
+; NEON-ENABLED-NEXT: ret
+;
+; NEON-DISABLED-LABEL: ui64_to_double:
+; NEON-DISABLED: // %bb.0: // %entry
+; NEON-DISABLED-NEXT: ldr x8, [x0]
+; NEON-DISABLED-NEXT: ucvtf d0, x8
+; NEON-DISABLED-NEXT: ret
+entry:
+ %ld = load i64, i64* %i, align 1
+ %conv = uitofp i64 %ld to double
+ ret double %conv
+}
+
+define float @ui64_to_float(i64* %i, float* %f) {
+; CHECK-LABEL: ui64_to_float:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: ucvtf s0, x8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i64, i64* %i, align 1
+ %conv = uitofp i64 %ld to float
+ ret float %conv
+}
+
+define half @ui64_to_half(i64* %i, half* %f) {
+; CHECK-LABEL: ui64_to_half:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: ucvtf h0, x8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i64, i64* %i, align 1
+ %conv = uitofp i64 %ld to half
+ ret half %conv
+}
+
+
+define double @si8_to_double(i8* %i, float* %f) {
+; CHECK-LABEL: si8_to_double:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldrsb w8, [x0]
+; CHECK-NEXT: scvtf d0, w8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i8, i8* %i, align 1
+ %conv = sitofp i8 %ld to double
+ ret double %conv
+}
+
+define float @si8_to_float(i8* %i, float* %f) {
+; CHECK-LABEL: si8_to_float:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldrsb w8, [x0]
+; CHECK-NEXT: scvtf s0, w8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i8, i8* %i, align 1
+ %conv = sitofp i8 %ld to float
+ ret float %conv
+}
+
+define half @si8_to_half(i8* %i, half* %f) {
+; CHECK-LABEL: si8_to_half:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldrsb w8, [x0]
+; CHECK-NEXT: scvtf h0, w8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i8, i8* %i, align 1
+ %conv = sitofp i8 %ld to half
+ ret half %conv
+}
+
+define double @si16_to_double(i16* %i, float* %f) {
+; CHECK-LABEL: si16_to_double:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldrsh w8, [x0]
+; CHECK-NEXT: scvtf d0, w8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i16, i16* %i, align 1
+ %conv = sitofp i16 %ld to double
+ ret double %conv
+}
+
+define float @si16_to_float(i16* %i, float* %f) {
+; CHECK-LABEL: si16_to_float:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr h0, [x0]
+; CHECK-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: ret
+entry:
+ %ld = load i16, i16* %i, align 1
+ %conv = sitofp i16 %ld to float
+ ret float %conv
+}
+
+define half @si16_to_half(i16* %i, half* %f) {
+; CHECK-LABEL: si16_to_half:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldrsh w8, [x0]
+; CHECK-NEXT: scvtf h0, w8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i16, i16* %i, align 1
+ %conv = sitofp i16 %ld to half
+ ret half %conv
+}
+
+define double @si32_to_double(i32* %i, float* %f) {
+; CHECK-LABEL: si32_to_double:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr s0, [x0]
+; CHECK-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-NEXT: scvtf d0, d0
+; CHECK-NEXT: ret
+entry:
+ %ld = load i32, i32* %i, align 1
+ %conv = sitofp i32 %ld to double
+ ret double %conv
+}
+
+define float @si32_to_float(i32* %i, float* %f) {
+; NEON-ENABLED-LABEL: si32_to_float:
+; NEON-ENABLED: // %bb.0: // %entry
+; NEON-ENABLED-NEXT: ldr s0, [x0]
+; NEON-ENABLED-NEXT: scvtf s0, s0
+; NEON-ENABLED-NEXT: ret
+;
+; NEON-DISABLED-LABEL: si32_to_float:
+; NEON-DISABLED: // %bb.0: // %entry
+; NEON-DISABLED-NEXT: ldr w8, [x0]
+; NEON-DISABLED-NEXT: scvtf s0, w8
+; NEON-DISABLED-NEXT: ret
+entry:
+ %ld = load i32, i32* %i, align 1
+ %conv = sitofp i32 %ld to float
+ ret float %conv
+}
+
+define half @si32_to_half(i32* %i, half* %f) {
+; CHECK-LABEL: si32_to_half:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: scvtf h0, w8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i32, i32* %i, align 1
+ %conv = sitofp i32 %ld to half
+ ret half %conv
+}
+
+define double @si64_to_double(i64* %i, float* %f) {
+; NEON-ENABLED-LABEL: si64_to_double:
+; NEON-ENABLED: // %bb.0: // %entry
+; NEON-ENABLED-NEXT: ldr d0, [x0]
+; NEON-ENABLED-NEXT: scvtf d0, d0
+; NEON-ENABLED-NEXT: ret
+;
+; NEON-DISABLED-LABEL: si64_to_double:
+; NEON-DISABLED: // %bb.0: // %entry
+; NEON-DISABLED-NEXT: ldr x8, [x0]
+; NEON-DISABLED-NEXT: scvtf d0, x8
+; NEON-DISABLED-NEXT: ret
+entry:
+ %ld = load i64, i64* %i, align 1
+ %conv = sitofp i64 %ld to double
+ ret double %conv
+}
+
+define float @si64_to_float(i64* %i, float* %f) {
+; CHECK-LABEL: si64_to_float:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: scvtf s0, x8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i64, i64* %i, align 1
+ %conv = sitofp i64 %ld to float
+ ret float %conv
+}
+
+define half @si64_to_half(i64* %i, half* %f) {
+; CHECK-LABEL: si64_to_half:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: scvtf h0, x8
+; CHECK-NEXT: ret
+entry:
+ %ld = load i64, i64* %i, align 1
+ %conv = sitofp i64 %ld to half
+ ret half %conv
+}
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