[PATCH] D125607: [DAG] Fold (shl (srl x, c), c) -> and(x, m) even if x has other uses

[Simon Pilgrim via Phabricator via llvm-commits]

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If we're using shift pairs to mask, then relax the one use limit if the shift amounts are equal - we'll only be generating a single AND node.

AArch64 has a couple of regressions due to this, so I've enforced the existing one use limit inside a AArch64TargetLowering::shouldFoldConstantShiftPairToMask callback.

Part of the work to fix the regressions in D77804 <https://reviews.llvm.org/D77804>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125607

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  llvm/test/CodeGen/AMDGPU/load-lo16.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/ARM/combine-movc-sub.ll
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
  llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll

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